class FASEDMemoryTimingModel extends BridgeModule[HostPortIO[FASEDTargetIO]] with UsesHostDRAM
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- FASEDMemoryTimingModel
- UsesHostDRAM
- HostDramHeaderConsts
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Instance Constructors
- new FASEDMemoryTimingModel(completeConfig: CompleteConfig, hostParams: Parameters)
Type Members
- class Impl extends BridgeModuleImp[HostPortIO[FASEDTargetIO]]
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
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- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- val cfg: BaseConfig
- var children: List[LazyModule]
- Attributes
- protected[diplomacy]
- Definition Classes
- LazyModule
- def childrenIterator(iterfunc: (LazyModule) => Unit): Unit
- Definition Classes
- LazyModule
- lazy val className: String
- Definition Classes
- LazyModule
- def clone(): AnyRef
- Attributes
- protected[lang]
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- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
- def cloneDangles(): List[Dangle]
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- protected[diplomacy]
- Definition Classes
- LazyModule
- var cloneProto: Option[LazyModule]
- Attributes
- protected[diplomacy]
- Definition Classes
- LazyModule
- val customSize: Option[BigInt]
- Definition Classes
- Widget
- lazy val desiredName: String
- Definition Classes
- LazyModule
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef → Any
- def getCRAddr(name: String): Int
- Definition Classes
- Widget
- def getChildren: List[LazyModule]
- Definition Classes
- LazyModule
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
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- @native() @IntrinsicCandidate()
- def getNodes: List[BaseNode]
- Definition Classes
- LazyModule
- def getSettings: String
Used by the runtime configuration generator, and not the main GG flow.
- def getWId: Int
- Definition Classes
- Widget
- def getWName: String
- Definition Classes
- Widget
- lazy val graphML: String
- Definition Classes
- LazyModule
- def hashCode(): Int
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
- val hostWidthBytes: Int
- var inModuleBody: List[() => Unit]
- Attributes
- protected[diplomacy]
- Definition Classes
- LazyModule
- var info: SourceInfo
- Attributes
- protected[diplomacy]
- Definition Classes
- LazyModule
- lazy val instanceName: String
- Definition Classes
- LazyModule
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- def line: String
- Definition Classes
- LazyModule
- def memRegionSize: BigInt
- Definition Classes
- Widget
- val memoryMasterNode: AXI4OutwardNode
The AXI4 master node the Bridge will use to present memory requests to its allocated DRAM.
The AXI4 master node the Bridge will use to present memory requests to its allocated DRAM.
- Definition Classes
- FASEDMemoryTimingModel → UsesHostDRAM
- val memoryRegionName: String
- Definition Classes
- FASEDMemoryTimingModel → HostDramHeaderConsts
- val memorySlaveConstraints: MemorySlaveConstraints
A specification for the memory region this Bridge wishes to be allocated.
A specification for the memory region this Bridge wishes to be allocated. See MemorySlaveConstraints for more explanation.
- Definition Classes
- FASEDMemoryTimingModel → UsesHostDRAM
- lazy val module: Impl
- Definition Classes
- FASEDMemoryTimingModel → BridgeModule → Widget → LazyModule
- lazy val moduleName: String
- Definition Classes
- LazyModule
- def name: String
- Definition Classes
- LazyModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def nodeIterator(iterfunc: (BaseNode) => Unit): Unit
- Definition Classes
- LazyModule
- var nodes: List[BaseNode]
- Attributes
- protected[diplomacy]
- Definition Classes
- LazyModule
- final def notify(): Unit
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- Annotations
- @native() @IntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- def omitGraphML: Boolean
- Definition Classes
- LazyModule
- implicit val p: Parameters
- Definition Classes
- FASEDMemoryTimingModel → LazyModule
- val parent: Option[LazyModule]
- Attributes
- protected[diplomacy]
- Definition Classes
- LazyModule
- def parents: Seq[LazyModule]
- Definition Classes
- LazyModule
- lazy val pathName: String
- Definition Classes
- LazyModule
- def printCRs: Unit
- Definition Classes
- Widget
- def settingsToString(settings: Seq[(String, BigInt)]): Seq[String]
Disambiguates between multiple fased instances by using wId (this increments for each instantion of widgets of the same class), which is defined in Widget
- def shouldBeInlined: Boolean
- Definition Classes
- LazyModule
- def suggestName(x: Option[String]): FASEDMemoryTimingModel.this.type
- Definition Classes
- LazyModule
- def suggestName(x: String): FASEDMemoryTimingModel.this.type
- Definition Classes
- LazyModule
- lazy val suggestedName: String
- Definition Classes
- LazyModule
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- val targetWidthBytes: Int
- val toHostDRAMNode: AXI4MasterNode
- def toString(): String
- Definition Classes
- AnyRef → Any
- val wId: Int
- Definition Classes
- Widget
- val wName: String
- Definition Classes
- Widget
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])