Packages

c

midas.models

LatencyHistogramUnitTest

class LatencyHistogramUnitTest extends UnitTest

Linear Supertypes
UnitTest, UnitTestLegacyModule, HasUnitTestIO, Module, RawModule, BaseModule, IsInstantiable, HasId, InstanceId, AnyRef, Any
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Inherited
  1. LatencyHistogramUnitTest
  2. UnitTest
  3. UnitTestLegacyModule
  4. HasUnitTestIO
  5. Module
  6. RawModule
  7. BaseModule
  8. IsInstantiable
  9. HasId
  10. InstanceId
  11. AnyRef
  12. Any
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new LatencyHistogramUnitTest()

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  8. val addrBits: Int
  9. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  10. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  11. final val clock: Clock
    Definition Classes
    Module
  12. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
  13. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  14. val cycleReq: Vec[Bool]
  15. val cycleResp: Vec[Bool]
  16. val dataBits: Int
  17. def desiredName: String
    Definition Classes
    BaseModule
  18. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  19. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  20. val expectedCount: UInt
  21. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  22. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  23. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  24. def hasSeed: Boolean
    Definition Classes
    HasId
  25. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  26. val histogram: HostLatencyHistogram
  27. val initValid: Bool
  28. val initValues: Vec[UInt]
  29. val initWriteIdx: UInt
  30. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  31. val io: Bundle with UnitTestIO
    Definition Classes
    UnitTestLegacyModule → HasUnitTestIO
  32. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  33. final lazy val name: String
    Definition Classes
    BaseModule
  34. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  35. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  36. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  37. def parentModName: String
    Definition Classes
    HasId → InstanceId
  38. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  39. def pathName: String
    Definition Classes
    HasId → InstanceId
  40. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  41. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  42. val readAddrs: Vec[UInt]
  43. val readCount: UInt
  44. val readData: UInt
  45. val readDone: Bool
  46. val readExpected: Vec[UInt]
  47. val readIdx: UInt
  48. val readValid: Bool
  49. val reqId: UInt
  50. final val reset: Reset
    Definition Classes
    Module
  51. val respId: UInt
  52. val runDone: Bool
  53. val runIdx: UInt
  54. val s_done: UInt
  55. val s_readInit: UInt
  56. val s_readout: UInt
  57. val s_run: UInt
  58. val s_start: UInt
  59. val state: UInt
  60. def suggestName(seed: => String): LatencyHistogramUnitTest.this.type
    Definition Classes
    HasId
  61. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  62. val testName: String
    Definition Classes
    UnitTest
  63. val timed_out: Bool
    Definition Classes
    UnitTest
  64. val timeout: Int
    Definition Classes
    UnitTest
  65. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  66. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  67. def toString(): String
    Definition Classes
    AnyRef → Any
  68. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  69. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  70. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  71. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable]) @Deprecated
    Deprecated
  2. def override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  3. def override_clock_=(rhs: Option[Clock]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  4. def override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  5. def override_reset_=(rhs: Option[Bool]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

Inherited from UnitTest

Inherited from UnitTestLegacyModule

Inherited from HasUnitTestIO

Inherited from Module

Inherited from RawModule

Inherited from BaseModule

Inherited from IsInstantiable

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

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