Packages

c

midas.widgets

MemorySlaveConstraints

case class MemorySlaveConstraints(address: Seq[AddressSet], supportsRead: TransferSizes, supportsWrite: TransferSizes) extends Product with Serializable

Constrains the "virtual" memory region as seen by Bridge.

address

AddressSets defining the addresses the bridge will access. These addresses may overlap with other bridges, Golden Gate will ensure isolation by using a base-and-bound scheme based on the range of the requested addresses. THe reqested addresses need not be contiguous and their union need not being at address 0. Currently non-contiguous regions will be allocated memory as though it were continguous.

supportsRead

TransferSize specifying the range of read transaction sizes this bridge will produce

supportsWrite

TransferSize specifying the range of write transaction sizes this bridge will produce Example. Request 4GiB of host DRAM, with read and write transactions that range between 1 and 64B: MemorySlaveConstraints(AddressSet(0, 0x3FFF_FFFF), TransferSizes(1, 64), TransferSizes(1, 64)) Q: Perhaps the last two parameters should be removed, and the bridge should be forced to work the slaves it is given?

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Instance Constructors

  1. new MemorySlaveConstraints(address: Seq[AddressSet], supportsRead: TransferSizes, supportsWrite: TransferSizes)

    address

    AddressSets defining the addresses the bridge will access. These addresses may overlap with other bridges, Golden Gate will ensure isolation by using a base-and-bound scheme based on the range of the requested addresses. THe reqested addresses need not be contiguous and their union need not being at address 0. Currently non-contiguous regions will be allocated memory as though it were continguous.

    supportsRead

    TransferSize specifying the range of read transaction sizes this bridge will produce

    supportsWrite

    TransferSize specifying the range of write transaction sizes this bridge will produce Example. Request 4GiB of host DRAM, with read and write transactions that range between 1 and 64B: MemorySlaveConstraints(AddressSet(0, 0x3FFF_FFFF), TransferSizes(1, 64), TransferSizes(1, 64)) Q: Perhaps the last two parameters should be removed, and the bridge should be forced to work the slaves it is given?

Value Members

  1. final def !=(arg0: Any): Boolean
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    AnyRef → Any
  2. final def ##: Int
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  3. final def ==(arg0: Any): Boolean
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  4. val address: Seq[AddressSet]
  5. final def asInstanceOf[T0]: T0
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  6. def clone(): AnyRef
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  10. final def ne(arg0: AnyRef): Boolean
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  11. final def notify(): Unit
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  12. final def notifyAll(): Unit
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    @native() @IntrinsicCandidate()
  13. def productElementNames: Iterator[String]
    Definition Classes
    Product
  14. val supportsRead: TransferSizes
  15. val supportsWrite: TransferSizes
  16. final def synchronized[T0](arg0: => T0): T0
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  17. final def wait(arg0: Long, arg1: Int): Unit
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  19. final def wait(): Unit
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  1. def finalize(): Unit
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    Deprecated

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