Packages

c

midas.models

DynamicLatencyPipe

class DynamicLatencyPipe[T <: Data] extends Module with HasFIFOPointers

Linear Supertypes
HasFIFOPointers, Module, RawModule, BaseModule, IsInstantiable, HasId, InstanceId, AnyRef, Any
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  1. Alphabetic
  2. By Inheritance
Inherited
  1. DynamicLatencyPipe
  2. HasFIFOPointers
  3. Module
  4. RawModule
  5. BaseModule
  6. IsInstantiable
  7. HasId
  8. InstanceId
  9. AnyRef
  10. Any
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new DynamicLatencyPipe(gen: T, entries: Int, countBits: Int)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  8. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  9. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  10. final val clock: Clock
    Definition Classes
    Module
  11. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
  12. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  13. val deq_ptr: Counter
    Definition Classes
    HasFIFOPointers
  14. def desiredName: String
    Definition Classes
    BaseModule
  15. val do_deq: Bool
    Definition Classes
    HasFIFOPointers
  16. val do_enq: Bool
    Definition Classes
    HasFIFOPointers
  17. val done: Vec[Bool]
  18. val empty: Bool
    Definition Classes
    HasFIFOPointers
  19. val enq_ptr: Counter
    Definition Classes
    HasFIFOPointers
  20. val entries: Int
    Definition Classes
    DynamicLatencyPipeHasFIFOPointers
  21. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  22. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  23. val full: Bool
    Definition Classes
    HasFIFOPointers
  24. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  25. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  26. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  27. def hasSeed: Boolean
    Definition Classes
    HasId
  28. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  29. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  30. val io: DynamicLatencyPipeIO[T]
  31. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  32. val latencies: Vec[UInt]
  33. val maybe_full: Bool
    Definition Classes
    HasFIFOPointers
  34. final lazy val name: String
    Definition Classes
    BaseModule
  35. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  36. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  37. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  38. def parentModName: String
    Definition Classes
    HasId → InstanceId
  39. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  40. def pathName: String
    Definition Classes
    HasId → InstanceId
  41. val pendingRegisters: Vec[Bool]
  42. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  43. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  44. val ptr_diff: UInt
  45. val ptr_match: Bool
    Definition Classes
    HasFIFOPointers
  46. val ram: Mem[T]
  47. final val reset: Reset
    Definition Classes
    Module
  48. def suggestName(seed: => String): DynamicLatencyPipe.this.type
    Definition Classes
    HasId
  49. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  50. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  51. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  52. def toString(): String
    Definition Classes
    AnyRef → Any
  53. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  54. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  55. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  56. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable]) @Deprecated
    Deprecated
  2. def override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  3. def override_clock_=(rhs: Option[Clock]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  4. def override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  5. def override_reset_=(rhs: Option[Bool]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

Inherited from HasFIFOPointers

Inherited from Module

Inherited from RawModule

Inherited from BaseModule

Inherited from IsInstantiable

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped