class RankStateTracker extends Module with HasDRAMMASConstants
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- HasDRAMMASConstants
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Instance Constructors
- new RankStateTracker(key: DramOrganizationParams)
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- final def !=(arg0: Any): Boolean
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- final def ##: Int
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- final def ==(arg0: Any): Boolean
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- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
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- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
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- var _closed: Boolean
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- def _compatAutoWrapPorts(): Unit
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- BaseModule
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- val backendLatencyBits: Int
- Definition Classes
- HasDRAMMASConstants
- val bankTrackers: Seq[BankStateTrackerIO]
- def circuitName: String
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- protected
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- HasId
- final val clock: Clock
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- def clone(): AnyRef
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- val compileOptions: CompileOptions
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- def desiredName: String
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- final def eq(arg0: AnyRef): Boolean
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- def getCommands: Seq[Command]
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- def getModulePorts: Seq[Data]
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- def hasSeed: Boolean
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- def hashCode(): Int
- Definition Classes
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- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- val io: RankStateTrackerIO
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val maxDRAMTimingBits: Int
- Definition Classes
- HasDRAMMASConstants
- final lazy val name: String
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
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- val nextLegalACT: DownCounter
- val nextLegalCASR: DownCounter
- val nextLegalCASW: DownCounter
- val nextLegalPRE: DownCounter
- final def notify(): Unit
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- final def notifyAll(): Unit
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- @native() @IntrinsicCandidate()
- val numBankStates: Int
- Definition Classes
- HasDRAMMASConstants
- val numRankStates: Int
- Definition Classes
- HasDRAMMASConstants
- def parentModName: String
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- HasId → InstanceId
- def parentPathName: String
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- HasId → InstanceId
- def pathName: String
- Definition Classes
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- def portsContains(elem: Data): Boolean
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- BaseModule
- def portsSize: Int
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- protected
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- BaseModule
- final val reset: Reset
- Definition Classes
- Module
- val state: UInt
- def suggestName(seed: => String): RankStateTracker.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- val tFAWcheck: Queue[UInt]
- val tREFI: UInt
- val tREFIBits: Int
- Definition Classes
- HasDRAMMASConstants
- val tREFIWidth: Int
- Definition Classes
- HasDRAMMASConstants
- val tRFCBits: Int
- Definition Classes
- HasDRAMMASConstants
- final def toAbsoluteTarget: IsModule
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- final def toNamed: ModuleName
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- def toString(): String
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- final def toTarget: ModuleTarget
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- final def wait(arg0: Long, arg1: Int): Unit
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- final def wait(): Unit
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- @throws(classOf[java.lang.InterruptedException])
- val wantREF: Bool
Deprecated Value Members
- def finalize(): Unit
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- def override_clock: Option[Clock]
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- Module
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
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- Module
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
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- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation