class FirstReadyFCFSModel extends TimingModel with HasDRAMMASConstants
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- FirstReadyFCFSModel
- HasDRAMMASConstants
- TimingModel
- HasNastiParameters
- EgressUnitParameters
- IngressModuleParameters
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Instance Constructors
- new FirstReadyFCFSModel(cfg: FirstReadyFCFSConfig)(implicit p: Parameters)
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
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- Definition Classes
- BaseModule
- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
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- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _compatAutoWrapPorts(): Unit
- Definition Classes
- BaseModule
- val actBank: UInt
- val actRank: UInt
- val actRow: UInt
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- val backend: DRAMBackend
- val backendLatencyBits: Int
- Definition Classes
- HasDRAMMASConstants
- val bankHasReadyEntries: Vec[Bool]
- def bytesToXSize(bytes: UInt): UInt
- Definition Classes
- HasNastiParameters
- val canLegallyACT: (FirstReadyFCFSEntry) => Bool
- val canLegallyCASR: (FirstReadyFCFSEntry) => Bool
- val canLegallyCASW: (FirstReadyFCFSEntry) => Bool
- val canLegallyPRE: (FirstReadyFCFSEntry) => Bool
- val casAutoPRE: Bool
- val cfg: BaseConfig
- Definition Classes
- TimingModel → IngressModuleParameters
- def checkRankBankLegality(getField: (CommandLegalBools) => Bool)(masEntry: FirstReadyFCFSEntry): Bool
- def circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- final val clock: Clock
- Definition Classes
- Module
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
- val cmdBank: UInt
- val cmdBankOH: UInt
- val cmdBusBusy: DownCounter
- val cmdMonitor: CommandBusMonitor
- val cmdRank: UInt
- val cmdRow: UInt
- val columnArbiter: Arbiter[FirstReadyFCFSEntry]
- val compileOptions: CompileOptions
- Definition Classes
- RawModule
- def desiredName: String
- Definition Classes
- BaseModule
- val egressUnitDelay: Int
- Definition Classes
- EgressUnitParameters
- val entriesStillReady: IndexedSeq[Bool]
- val entryWantsACT: IndexedSeq[Bool]
- val entryWantsPRE: IndexedSeq[Bool]
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
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- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
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- Annotations
- @native() @IntrinsicCandidate()
- def getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- def hasSeed: Boolean
- Definition Classes
- HasId
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- val ingressARQdepth: Int
- Definition Classes
- IngressModuleParameters
- val ingressAWQdepth: Int
- Definition Classes
- IngressModuleParameters
- val ingressWQdepth: Int
- Definition Classes
- IngressModuleParameters
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- lazy val io: FirstReadyFCFSIO
- Definition Classes
- FirstReadyFCFSModel → TimingModel
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val longName: String
- Definition Classes
- FirstReadyFCFSModel → TimingModel
- val maxDRAMTimingBits: Int
- Definition Classes
- HasDRAMMASConstants
- val memReqDone: Bool
- val monitor: MemoryModelMonitor
- Definition Classes
- TimingModel
- final lazy val name: String
- Definition Classes
- BaseModule
- val nastiARUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiAWUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiBUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiExternal: NastiParameters
- Definition Classes
- HasNastiParameters
- val nastiRIdBits: Int
- Definition Classes
- HasNastiParameters
- val nastiRUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiReq: NastiReqChannels
- Definition Classes
- TimingModel
- val nastiReqIden: IdentityModule[NastiReqChannels]
- Definition Classes
- TimingModel
- val nastiWIdBits: Int
- Definition Classes
- HasNastiParameters
- val nastiWStrobeBits: Int
- Definition Classes
- HasNastiParameters
- val nastiWUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXAddrBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXBurstBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXCacheBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXDataBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXIdBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXLenBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXProtBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXQosBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXRegionBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXRespBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXSizeBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXUserBits: Int
- Definition Classes
- HasNastiParameters
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- val newRefAddrMatch: Bool
- val newRefBankAddrMatch: Bool
- val newReference: DecoupledIO[FirstReadyFCFSEntry]
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- val numBankStates: Int
- Definition Classes
- HasDRAMMASConstants
- val numRankStates: Int
- Definition Classes
- HasDRAMMASConstants
- val otherReadyEntries: Bool
- implicit val p: Parameters
- Definition Classes
- TimingModel → HasNastiParameters → IngressModuleParameters
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- val pendingAWReq: SatUpDownCounterIO
- Definition Classes
- TimingModel
- val pendingReads: SatUpDownCounterIO
- Definition Classes
- TimingModel
- val pendingWReq: SatUpDownCounterIO
- Definition Classes
- TimingModel
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- val powerStats: Seq[RankPowerIO]
- val preBank: UInt
- val preRank: UInt
- def printGenerationConfig: Unit
- Definition Classes
- TimingModel
- def printTimingModelGenerationConfig: Unit
- Definition Classes
- FirstReadyFCFSModel → TimingModel
- val rResp: DecoupledIO[ReadResponseMetaData]
- Definition Classes
- TimingModel
- val rankStateTrackers: Seq[RankStateTracker]
- def rankWantsRef(rankAddrOH: UInt): Bool
- val refBuffer: CollapsingBuffer[FirstReadyFCFSEntry]
- val refList: Vec[Valid[FirstReadyFCFSEntry]]
- val refUpdates: Vec[Valid[FirstReadyFCFSEntry]]
- val refreshUnit: RankRefreshUnitIO
- final val reset: Reset
- Definition Classes
- Module
- val rowHitsInRank: Vec[UInt]
- val selectedCmd: UInt
- val suggestAct: Bool
- def suggestName(seed: => String): FirstReadyFCFSModel.this.type
- Definition Classes
- HasId
- val suggestPre: Bool
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- val tCycle: UInt
- Definition Classes
- TimingModel
- val tNasti: NastiIO
************************** CHISEL BEGINS ********************************
************************** CHISEL BEGINS ********************************
- Definition Classes
- TimingModel
- val tREFIBits: Int
- Definition Classes
- HasDRAMMASConstants
- val tREFIWidth: Int
- Definition Classes
- HasDRAMMASConstants
- val tRFCBits: Int
- Definition Classes
- HasDRAMMASConstants
- val timings: DRAMProgrammableTimings
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- val wResp: DecoupledIO[WriteResponseMetaData]
- Definition Classes
- TimingModel
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- val xactionRelease: AXI4Releaser
- Definition Classes
- TimingModel
- val xactionScheduler: UnifiedFIFOXactionScheduler
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- def override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation