abstract class BaseDRAMMMRegIO extends MMRegIO with HasConsoleUtils
Linear Supertypes
Known Subclasses
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Inherited
- BaseDRAMMMRegIO
- HasConsoleUtils
- MMRegIO
- HasProgrammableRegisters
- Bundle
- Record
- Aggregate
- Data
- SourceInfoDoc
- NamedComponent
- HasId
- InstanceId
- AnyRef
- Any
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Visibility
- Public
- Protected
Instance Constructors
-  new BaseDRAMMMRegIO(cfg: DRAMBaseConfig)
Abstract Value Members
-   abstract  def registers: Seq[(Data, IsRuntimeSetting)]- Definition Classes
- HasProgrammableRegisters
 
-   abstract  def requestSettings(): Unit- Definition Classes
- MMRegIO
 
Concrete Value Members
-   final  def !=(arg0: Any): Boolean- Definition Classes
- AnyRef → Any
 
-   final  def ##: Int- Definition Classes
- AnyRef → Any
 
-   final  def :=(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit- Definition Classes
- Data
 
-   final  def <>(that: => Data)(implicit sourceInfo: SourceInfo, connectionCompileOptions: CompileOptions): Unit- Definition Classes
- Data
 
-   final  def ==(arg0: Any): Boolean- Definition Classes
- AnyRef → Any
 
-    def _cloneTypeImpl: Record- Attributes
- protected
- Definition Classes
- Record
 
-    def _elementsImpl: Iterable[(String, Any)]- Attributes
- protected
- Definition Classes
- Bundle
 
-    def _usingPlugin: Boolean- Attributes
- protected
- Definition Classes
- Bundle
 
-   final  def asInstanceOf[T0]: T0- Definition Classes
- Any
 
-   macro  def asTypeOf[T <: Data](that: T): T- Definition Classes
- Data
 
-   final macro  def asUInt: UInt- Definition Classes
- Data
 
-    def autoSeed(name: String): BaseDRAMMMRegIO.this.type- Definition Classes
- Data → HasId
 
-  val backendLatency: UInt
-  val bankAddr: ProgrammableSubAddr
-    def binding: Option[Binding]- Attributes
- protected[chisel3]
- Definition Classes
- Data
 
-    def binding_=(target: Binding): Unit- Attributes
- protected
- Definition Classes
- Data
 
-    val bins: Int- Definition Classes
- MMRegIO
 
-    def circuitName: String- Attributes
- protected
- Definition Classes
- HasId
 
-    def className: String- Definition Classes
- Bundle → Record
 
-    def clone(): AnyRef- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
 
-    def cloneType: BaseDRAMMMRegIO.this.type- Definition Classes
- Record → Data
 
-  val defaultRowOffset: BigInt
-    def do_asTypeOf[T <: Data](that: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T- Definition Classes
- Data
 
-    def do_asUInt(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): UInt- Definition Classes
- Aggregate → Data
 
-  val dramBaseRegisters: Seq[(UInt, RuntimeSetting)]
-  val dramTimings: DRAMProgrammableTimings
-   final  lazy val elements: SeqMap[String, Data]- Definition Classes
- Bundle → Record
 
-   final  def eq(arg0: AnyRef): Boolean- Definition Classes
- AnyRef
 
-    def equals(that: Any): Boolean- Definition Classes
- HasId → AnyRef → Any
 
-  def getAddressScheme(numRanks: BigInt, numBanks: BigInt, numRows: BigInt, numBytesPerLine: BigInt, pageSize: BigInt): Unit
-   final  def getClass(): Class[_ <: AnyRef]- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
 
-    def getDefaults(prefix: String = ""): Seq[(String, BigInt)]- Definition Classes
- HasProgrammableRegisters
 
-    def getElements: Seq[Data]- Definition Classes
- Record → Aggregate
 
-    def getName(dat: Data): String- Definition Classes
- HasProgrammableRegisters
 
-    def getSettings(prefix: String = ""): Seq[(String, BigInt)]- Definition Classes
- HasProgrammableRegisters
 
-  def getSpeedGrade(): String
-    def getTimingModelSettings(): Seq[(String, BigInt)]- Definition Classes
- MMRegIO
 
-   final  def getWidth: Int- Definition Classes
- Data
 
-    def hasSeed: Boolean- Definition Classes
- HasId
 
-    def hashCode(): Int- Definition Classes
- HasId → AnyRef → Any
 
-    def ignoreSeq: Boolean- Definition Classes
- Bundle
 
-    def instanceName: String- Definition Classes
- HasId → InstanceId
 
-   final  def isInstanceOf[T0]: Boolean- Definition Classes
- Any
 
-    def isLit: Boolean- Definition Classes
- Data
 
-   final  def isWidthKnown: Boolean- Definition Classes
- Data
 
-    def litOption: Option[BigInt]- Definition Classes
- Aggregate → Data
 
-    def litValue: BigInt- Definition Classes
- Aggregate → Data
 
-    val llc: Option[LLCProgrammableSettings]- Definition Classes
- MMRegIO
 
-  def lookupPart(density: BigInt, dqWidth: BigInt, speedGrade: String): Map[String, JSONField]
-   final  def ne(arg0: AnyRef): Boolean- Definition Classes
- AnyRef
 
-   final  def notify(): Unit- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
 
-   final  def notifyAll(): Unit- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
 
-  val openPagePolicy: Bool
-    def parentModName: String- Definition Classes
- HasId → InstanceId
 
-    def parentPathName: String- Definition Classes
- HasId → InstanceId
 
-    def pathName: String- Definition Classes
- HasId → InstanceId
 
-  val rankAddr: ProgrammableSubAddr
-  val rankPower: Vec[RankPowerIO]
-    val readOutstandingHistogram: Vec[UInt]- Definition Classes
- MMRegIO
 
-    lazy val regMap: Map[Data, IsRuntimeSetting]- Definition Classes
- HasProgrammableRegisters
 
-    def requestInput(query: String, default: BigInt, min: Option[BigInt] = None, max: Option[BigInt] = None): BigInt- Definition Classes
- HasConsoleUtils
 
-    def requestSeqSelection(header: String, possibilities: Seq[String], footer: String = "Selection number", default: BigInt = 0): Int- Definition Classes
- HasConsoleUtils
 
-  val rowAddr: ProgrammableSubAddr
-  def setBaseDRAMSettings(): Unit
-    def setUnboundSettings(prefix: String = "test"): Unit- Definition Classes
- HasProgrammableRegisters
 
-  val speedGrades: Seq[(String, String)]
-    def suggestName(seed: => String): BaseDRAMMMRegIO.this.type- Definition Classes
- HasId
 
-   final  def synchronized[T0](arg0: => T0): T0- Definition Classes
- AnyRef
 
-    val targetCycle: Option[UInt]- Definition Classes
- MMRegIO
 
-   final  def toAbsoluteTarget: ReferenceTarget- Definition Classes
- NamedComponent → InstanceId
 
-   final  def toNamed: ComponentName- Definition Classes
- NamedComponent → InstanceId
 
-    def toPrintable: Printable- Definition Classes
- Bundle → Record → Data
 
-    def toString(): String- Definition Classes
- Record → AnyRef → Any
 
-   final  def toTarget: ReferenceTarget- Definition Classes
- NamedComponent → InstanceId
 
-    val totalReadBeats: Option[UInt]- Definition Classes
- MMRegIO
 
-    val totalReads: Option[UInt]- Definition Classes
- MMRegIO
 
-    val totalWriteBeats: Option[UInt]- Definition Classes
- MMRegIO
 
-    val totalWrites: Option[UInt]- Definition Classes
- MMRegIO
 
-   final  def wait(arg0: Long, arg1: Int): Unit- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
 
-   final  def wait(arg0: Long): Unit- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
 
-   final  def wait(): Unit- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
 
-   final  def widthOption: Option[Int]- Definition Classes
- Data
 
-    val writeOutstandingHistogram: Vec[UInt]- Definition Classes
- MMRegIO