class BankConflictModel extends SplitTransactionModel
Linear Supertypes
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Inherited
- BankConflictModel
- SplitTransactionModel
- TimingModel
- HasNastiParameters
- EgressUnitParameters
- IngressModuleParameters
- Module
- RawModule
- BaseModule
- IsInstantiable
- HasId
- InstanceId
- AnyRef
- Any
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Visibility
- Public
- Protected
Instance Constructors
- new BankConflictModel(cfg: BankConflictConfig)(implicit p: Parameters)
Value Members
- def _compatAutoWrapPorts(): Unit
- Definition Classes
- BaseModule
- val awQueue: Queue[NastiWriteAddressChannel]
- Definition Classes
- SplitTransactionModel
- val bankBusyCycles: Seq[UInt]
- val bankConflictCounts: Vec[UInt]
- def bytesToXSize(bytes: UInt): UInt
- Definition Classes
- HasNastiParameters
- val cfg: BaseConfig
- Definition Classes
- TimingModel → IngressModuleParameters
- final val clock: Clock
- Definition Classes
- Module
- val compileOptions: CompileOptions
- Definition Classes
- RawModule
- val completedRef: BankQueueEntry
- val conflictPenalty: UInt
- def desiredName: String
- Definition Classes
- BaseModule
- val egressUnitDelay: Int
- Definition Classes
- EgressUnitParameters
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- def hasSeed: Boolean
- Definition Classes
- HasId
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- val ingressARQdepth: Int
- Definition Classes
- IngressModuleParameters
- val ingressAWQdepth: Int
- Definition Classes
- IngressModuleParameters
- val ingressWQdepth: Int
- Definition Classes
- IngressModuleParameters
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- lazy val io: BankConflictIO
************************** CHISEL BEGINS ********************************
************************** CHISEL BEGINS ********************************
- Definition Classes
- BankConflictModel → SplitTransactionModel → TimingModel
- val latency: UInt
- val longName: String
- Definition Classes
- BankConflictModel → TimingModel
- val marginalCycles: UInt
- val monitor: MemoryModelMonitor
- Definition Classes
- TimingModel
- final lazy val name: String
- Definition Classes
- BaseModule
- val nastiARUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiAWUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiBUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiExternal: NastiParameters
- Definition Classes
- HasNastiParameters
- val nastiRIdBits: Int
- Definition Classes
- HasNastiParameters
- val nastiRUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiReq: NastiReqChannels
- Definition Classes
- TimingModel
- val nastiReqIden: IdentityModule[NastiReqChannels]
- Definition Classes
- TimingModel
- val nastiWIdBits: Int
- Definition Classes
- HasNastiParameters
- val nastiWStrobeBits: Int
- Definition Classes
- HasNastiParameters
- val nastiWUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXAddrBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXBurstBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXCacheBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXDataBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXIdBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXLenBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXProtBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXQosBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXRegionBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXRespBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXSizeBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXUserBits: Int
- Definition Classes
- HasNastiParameters
- val newReference: DecoupledIO[BankConflictReference]
- val newWReq: Bool
- Definition Classes
- SplitTransactionModel
- implicit val p: Parameters
- Definition Classes
- TimingModel → HasNastiParameters → IngressModuleParameters
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- val pendingAWReq: SatUpDownCounterIO
- Definition Classes
- TimingModel
- val pendingReads: SatUpDownCounterIO
- Definition Classes
- TimingModel
- val pendingWReq: SatUpDownCounterIO
- Definition Classes
- TimingModel
- def printGenerationConfig: Unit
- Definition Classes
- TimingModel
- def printTimingModelGenerationConfig: Unit
- Definition Classes
- BankConflictModel → TimingModel
- val rResp: DecoupledIO[ReadResponseMetaData]
- Definition Classes
- TimingModel
- val refBuffer: CollapsingBuffer[BankConflictReference]
- val refList: Vec[Valid[BankConflictReference]]
- val refUpdates: Vec[Valid[BankConflictReference]]
- final val reset: Reset
- Definition Classes
- Module
- val selector: Arbiter[BankConflictReference]
- def suggestName(seed: => String): BankConflictModel.this.type
- Definition Classes
- HasId
- val tCycle: UInt
- Definition Classes
- TimingModel
- val tNasti: NastiIO
************************** CHISEL BEGINS ********************************
************************** CHISEL BEGINS ********************************
- Definition Classes
- TimingModel
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- val transactionQueue: Queue[BankQueueEntry]
- val transactionQueueArb: RRArbiter[BankQueueEntry]
- val wResp: DecoupledIO[WriteResponseMetaData]
- Definition Classes
- TimingModel
- val xactionRelease: AXI4Releaser
- Definition Classes
- TimingModel