class BankConflictModel extends SplitTransactionModel
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- BankConflictModel
- SplitTransactionModel
- TimingModel
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Instance Constructors
- new BankConflictModel(cfg: BankConflictConfig)(implicit p: Parameters)
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
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- final def ##: Int
- Definition Classes
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- final def ==(arg0: Any): Boolean
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- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
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- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
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- def _compatAutoWrapPorts(): Unit
- Definition Classes
- BaseModule
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- val awQueue: Queue[NastiWriteAddressChannel]
- Definition Classes
- SplitTransactionModel
- val bankBusyCycles: Seq[UInt]
- val bankConflictCounts: Vec[UInt]
- def bytesToXSize(bytes: UInt): UInt
- Definition Classes
- HasNastiParameters
- val cfg: BaseConfig
- Definition Classes
- TimingModel → IngressModuleParameters
- def circuitName: String
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- protected
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- final val clock: Clock
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- def clone(): AnyRef
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- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
- val compileOptions: CompileOptions
- Definition Classes
- RawModule
- val completedRef: BankQueueEntry
- val conflictPenalty: UInt
- def desiredName: String
- Definition Classes
- BaseModule
- val egressUnitDelay: Int
- Definition Classes
- EgressUnitParameters
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
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- final def getClass(): Class[_ <: AnyRef]
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- def getCommands: Seq[Command]
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- def getModulePorts: Seq[Data]
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- protected[chisel3]
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- BaseModule
- def hasSeed: Boolean
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- def hashCode(): Int
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- val ingressARQdepth: Int
- Definition Classes
- IngressModuleParameters
- val ingressAWQdepth: Int
- Definition Classes
- IngressModuleParameters
- val ingressWQdepth: Int
- Definition Classes
- IngressModuleParameters
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- lazy val io: BankConflictIO
************************** CHISEL BEGINS ********************************
************************** CHISEL BEGINS ********************************
- Definition Classes
- BankConflictModel → SplitTransactionModel → TimingModel
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val latency: UInt
- val longName: String
- Definition Classes
- BankConflictModel → TimingModel
- val marginalCycles: UInt
- val monitor: MemoryModelMonitor
- Definition Classes
- TimingModel
- final lazy val name: String
- Definition Classes
- BaseModule
- val nastiARUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiAWUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiBUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiExternal: NastiParameters
- Definition Classes
- HasNastiParameters
- val nastiRIdBits: Int
- Definition Classes
- HasNastiParameters
- val nastiRUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiReq: NastiReqChannels
- Definition Classes
- TimingModel
- val nastiReqIden: IdentityModule[NastiReqChannels]
- Definition Classes
- TimingModel
- val nastiWIdBits: Int
- Definition Classes
- HasNastiParameters
- val nastiWStrobeBits: Int
- Definition Classes
- HasNastiParameters
- val nastiWUserBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXAddrBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXBurstBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXCacheBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXDataBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXIdBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXLenBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXProtBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXQosBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXRegionBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXRespBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXSizeBits: Int
- Definition Classes
- HasNastiParameters
- val nastiXUserBits: Int
- Definition Classes
- HasNastiParameters
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- val newReference: DecoupledIO[BankConflictReference]
- val newWReq: Bool
- Definition Classes
- SplitTransactionModel
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- implicit val p: Parameters
- Definition Classes
- TimingModel → HasNastiParameters → IngressModuleParameters
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- val pendingAWReq: SatUpDownCounterIO
- Definition Classes
- TimingModel
- val pendingReads: SatUpDownCounterIO
- Definition Classes
- TimingModel
- val pendingWReq: SatUpDownCounterIO
- Definition Classes
- TimingModel
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- def printGenerationConfig: Unit
- Definition Classes
- TimingModel
- def printTimingModelGenerationConfig: Unit
- Definition Classes
- BankConflictModel → TimingModel
- val rResp: DecoupledIO[ReadResponseMetaData]
- Definition Classes
- TimingModel
- val refBuffer: CollapsingBuffer[BankConflictReference]
- val refList: Vec[Valid[BankConflictReference]]
- val refUpdates: Vec[Valid[BankConflictReference]]
- final val reset: Reset
- Definition Classes
- Module
- val selector: Arbiter[BankConflictReference]
- def suggestName(seed: => String): BankConflictModel.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- val tCycle: UInt
- Definition Classes
- TimingModel
- val tNasti: NastiIO
************************** CHISEL BEGINS ********************************
************************** CHISEL BEGINS ********************************
- Definition Classes
- TimingModel
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- val transactionQueue: Queue[BankQueueEntry]
- val transactionQueueArb: RRArbiter[BankQueueEntry]
- val wResp: DecoupledIO[WriteResponseMetaData]
- Definition Classes
- TimingModel
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- val xactionRelease: AXI4Releaser
- Definition Classes
- TimingModel
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
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- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- def override_clock: Option[Clock]
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
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- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
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- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation