Packages

c

midas.models

BankConflictModel

class BankConflictModel extends SplitTransactionModel

Linear Supertypes
SplitTransactionModel, TimingModel, HasNastiParameters, EgressUnitParameters, IngressModuleParameters, Module, RawModule, BaseModule, IsInstantiable, HasId, InstanceId, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. BankConflictModel
  2. SplitTransactionModel
  3. TimingModel
  4. HasNastiParameters
  5. EgressUnitParameters
  6. IngressModuleParameters
  7. Module
  8. RawModule
  9. BaseModule
  10. IsInstantiable
  11. HasId
  12. InstanceId
  13. AnyRef
  14. Any
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new BankConflictModel(cfg: BankConflictConfig)(implicit p: Parameters)

Value Members

  1. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  2. val awQueue: Queue[NastiWriteAddressChannel]
    Definition Classes
    SplitTransactionModel
  3. val bankBusyCycles: Seq[UInt]
  4. val bankConflictCounts: Vec[UInt]
  5. def bytesToXSize(bytes: UInt): UInt
    Definition Classes
    HasNastiParameters
  6. val cfg: BaseConfig
    Definition Classes
    TimingModelIngressModuleParameters
  7. final val clock: Clock
    Definition Classes
    Module
  8. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  9. val completedRef: BankQueueEntry
  10. val conflictPenalty: UInt
  11. def desiredName: String
    Definition Classes
    BaseModule
  12. val egressUnitDelay: Int
    Definition Classes
    EgressUnitParameters
  13. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  14. def hasSeed: Boolean
    Definition Classes
    HasId
  15. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  16. val ingressARQdepth: Int
    Definition Classes
    IngressModuleParameters
  17. val ingressAWQdepth: Int
    Definition Classes
    IngressModuleParameters
  18. val ingressWQdepth: Int
    Definition Classes
    IngressModuleParameters
  19. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  20. lazy val io: BankConflictIO

    ************************** CHISEL BEGINS ********************************

    ************************** CHISEL BEGINS ********************************

    Definition Classes
    BankConflictModelSplitTransactionModelTimingModel
  21. val latency: UInt
  22. val longName: String
    Definition Classes
    BankConflictModelTimingModel
  23. val marginalCycles: UInt
  24. val monitor: MemoryModelMonitor
    Definition Classes
    TimingModel
  25. final lazy val name: String
    Definition Classes
    BaseModule
  26. val nastiARUserBits: Int
    Definition Classes
    HasNastiParameters
  27. val nastiAWUserBits: Int
    Definition Classes
    HasNastiParameters
  28. val nastiBUserBits: Int
    Definition Classes
    HasNastiParameters
  29. val nastiExternal: NastiParameters
    Definition Classes
    HasNastiParameters
  30. val nastiRIdBits: Int
    Definition Classes
    HasNastiParameters
  31. val nastiRUserBits: Int
    Definition Classes
    HasNastiParameters
  32. val nastiReq: NastiReqChannels
    Definition Classes
    TimingModel
  33. val nastiReqIden: IdentityModule[NastiReqChannels]
    Definition Classes
    TimingModel
  34. val nastiWIdBits: Int
    Definition Classes
    HasNastiParameters
  35. val nastiWStrobeBits: Int
    Definition Classes
    HasNastiParameters
  36. val nastiWUserBits: Int
    Definition Classes
    HasNastiParameters
  37. val nastiXAddrBits: Int
    Definition Classes
    HasNastiParameters
  38. val nastiXBurstBits: Int
    Definition Classes
    HasNastiParameters
  39. val nastiXCacheBits: Int
    Definition Classes
    HasNastiParameters
  40. val nastiXDataBits: Int
    Definition Classes
    HasNastiParameters
  41. val nastiXIdBits: Int
    Definition Classes
    HasNastiParameters
  42. val nastiXLenBits: Int
    Definition Classes
    HasNastiParameters
  43. val nastiXProtBits: Int
    Definition Classes
    HasNastiParameters
  44. val nastiXQosBits: Int
    Definition Classes
    HasNastiParameters
  45. val nastiXRegionBits: Int
    Definition Classes
    HasNastiParameters
  46. val nastiXRespBits: Int
    Definition Classes
    HasNastiParameters
  47. val nastiXSizeBits: Int
    Definition Classes
    HasNastiParameters
  48. val nastiXUserBits: Int
    Definition Classes
    HasNastiParameters
  49. val newReference: DecoupledIO[BankConflictReference]
  50. val newWReq: Bool
    Definition Classes
    SplitTransactionModel
  51. implicit val p: Parameters
  52. def parentModName: String
    Definition Classes
    HasId → InstanceId
  53. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  54. def pathName: String
    Definition Classes
    HasId → InstanceId
  55. val pendingAWReq: SatUpDownCounterIO
    Definition Classes
    TimingModel
  56. val pendingReads: SatUpDownCounterIO
    Definition Classes
    TimingModel
  57. val pendingWReq: SatUpDownCounterIO
    Definition Classes
    TimingModel
  58. def printGenerationConfig: Unit
    Definition Classes
    TimingModel
  59. def printTimingModelGenerationConfig: Unit
    Definition Classes
    BankConflictModelTimingModel
  60. val rResp: DecoupledIO[ReadResponseMetaData]
    Definition Classes
    TimingModel
  61. val refBuffer: CollapsingBuffer[BankConflictReference]
  62. val refList: Vec[Valid[BankConflictReference]]
  63. val refUpdates: Vec[Valid[BankConflictReference]]
  64. final val reset: Reset
    Definition Classes
    Module
  65. val selector: Arbiter[BankConflictReference]
  66. def suggestName(seed: => String): BankConflictModel.this.type
    Definition Classes
    HasId
  67. val tCycle: UInt
    Definition Classes
    TimingModel
  68. val tNasti: NastiIO

    ************************** CHISEL BEGINS ********************************

    ************************** CHISEL BEGINS ********************************

    Definition Classes
    TimingModel
  69. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  70. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  71. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  72. val transactionQueue: Queue[BankQueueEntry]
  73. val transactionQueueArb: RRArbiter[BankQueueEntry]
  74. val wResp: DecoupledIO[WriteResponseMetaData]
    Definition Classes
    TimingModel
  75. val xactionRelease: AXI4Releaser
    Definition Classes
    TimingModel