class Impl extends BridgeModuleImp[HostPortIO[FASEDTargetIO]]
Linear Supertypes
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Inherited
- Impl
- BridgeModuleImp
- WidgetImp
- LazyModuleImp
- LazyModuleImpLike
- Module
- RawModule
- BaseModule
- IsInstantiable
- HasId
- InstanceId
- AnyRef
- Any
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Visibility
- Public
- Protected
Instance Constructors
- new Impl()
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
- Attributes
- protected
- Definition Classes
- BaseModule
- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
- Attributes
- protected
- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _compatAutoWrapPorts(): Unit
- Definition Classes
- BaseModule
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def attach(reg: Data, name: String, permissions: Permissions = ReadWrite, substruct: Boolean = true): Int
- Definition Classes
- WidgetImp
- def attachDecoupledSink(channel: DecoupledIO[UInt], name: String, substruct: Boolean = true): Int
- Definition Classes
- WidgetImp
- def attachDecoupledSource(channel: DecoupledIO[UInt], name: String, substruct: Boolean = true): Int
- Definition Classes
- WidgetImp
- def attachIO(io: Record, prefix: String = ""): Unit
- Definition Classes
- WidgetImp
- val auto: AutoBundle
- Definition Classes
- LazyModuleImp → LazyModuleImpLike
- val bReady: Bool
- val brespError: UInt
- def circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- final val clock: Clock
- Definition Classes
- Module
- def clockDomainInfo: RationalClock
- Definition Classes
- BridgeModuleImp
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
- val compileOptions: CompileOptions
- Definition Classes
- RawModule
- val crRegistry: MCRFileMap
- Definition Classes
- WidgetImp
- val ctrlWidth: Int
- Definition Classes
- WidgetImp
- val dangles: List[Dangle]
- Definition Classes
- LazyModuleImp → LazyModuleImpLike
- def desiredName: String
- Definition Classes
- LazyModuleImpLike → BaseModule
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- val funcModelRegs: FuncModelProgrammableRegs
- val gate: AbstractClockGate
- def genAndAttachQueue(channel: DecoupledIO[UInt], name: String, depth: Int = 2): DecoupledIO[UInt]
- Definition Classes
- WidgetImp
- def genAndAttachReg[T <: Data](wire: T, name: String, default: Option[T] = None, masterDriven: Boolean = true, substruct: Boolean = true): T
- Definition Classes
- WidgetImp
- def genCRFile(): MCRFile
- Definition Classes
- WidgetImp
- def genConstructor(base: BigInt, sb: StringBuilder, bridgeDriverClassName: String, bridgeDriverHeaderName: String, args: Seq[CPPLiteral] = Seq(), guard: String = "GET_BRIDGE_CONSTRUCTOR", hasStreams: Boolean = false, hasLoadMem: Boolean = false, hasMMIOAddrMap: Boolean = false): Unit
Emits a call to the construction into the generated header.
Emits a call to the construction into the generated header.
- base
The base address of the MMIO region allocated to the widget.
- sb
The string builder to append to.
- bridgeDriverClassName
Name of the bridge driver class.
- bridgeDriverHeaderName
Name of the header to get the driver from.
- args
List of C++ literals to pass as arguments.
- guard
Name of the header guard, used to order constructor calls.
- hasStreams
Flag indicating that a stream engine reference should be provided.
- hasLoadMem
Flag indicating that a loadmem widget reference should be provided.
- hasMMIOAddrMap
Flag indicating that an address map should be provided.
- Definition Classes
- WidgetImp
- def genHeader(base: BigInt, memoryRegions: Map[String, BigInt], sb: StringBuilder): Unit
Emits a header snippet for this widget.
Emits a header snippet for this widget.
- base
The base address of the MMIO region allocated to the widget.
- memoryRegions
A mapping of names to allocated FPGA-DRAM regions. This is one mechanism for establishing side-channels between two otherwise unconnected bridges or widgets.
- def genROReg[T <: Data](wire: T, name: String, substruct: Boolean = true): T
- Definition Classes
- WidgetImp
- def genRORegInit[T <: Data](wire: T, name: String, default: T, substruct: Boolean = true): T
- Definition Classes
- WidgetImp
- def genWOReg[T <: Data](wire: T, name: String, substruct: Boolean = true): T
- Definition Classes
- WidgetImp
- def genWORegInit[T <: Data](wire: T, name: String, default: T, substruct: Boolean = true): T
- Definition Classes
- WidgetImp
- def genWideRORegInit[T <: Bits](default: T, name: String, substruct: Boolean = true): T
- Definition Classes
- WidgetImp
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
- def getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- val hOutstandingReads: SatUpDownCounterIO
- val hOutstandingWrites: SatUpDownCounterIO
- val hPort: HostPortIO[FASEDTargetIO]
- Definition Classes
- Impl → BridgeModuleImp
- def hasSeed: Boolean
- Definition Classes
- HasId
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- val host_mem_idle: Bool
- val ingress: IngressModule
- val ingressReady: Bool
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- def instantiate(): (AutoBundle, List[Dangle])
- Attributes
- protected[diplomacy]
- Definition Classes
- LazyModuleImpLike
- val io: WidgetIO
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val model: TimingModel
- final lazy val name: String
- Definition Classes
- BaseModule
- val nastiToHostDRAM: NastiIO
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- def numChunks(e: Bits): Int
- Definition Classes
- WidgetImp
- def numRegs: Int
- Definition Classes
- WidgetImp
- implicit val p: Parameters
- Definition Classes
- LazyModuleImpLike
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- val rReady: Bool
- val readEgress: ReadEgress
- final val reset: Reset
- Definition Classes
- Module
- val rrespError: UInt
- def suggestName(seed: => String): Impl.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- val tFireHelper: DecoupledHelper
- val tNasti: NastiIO
- val tReset: Bool
- val tResetReady: Bool
- val targetFire: Bool
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- val toHostDRAM: AXI4Bundle
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- val wrapper: LazyModule
- Definition Classes
- LazyModuleImp → LazyModuleImpLike
- val writeEgress: WriteEgress
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- def override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation