class RankPowerMonitor extends Module with HasDRAMMASConstants
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- new RankPowerMonitor(key: DramOrganizationParams)
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- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
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- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
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- val backendLatencyBits: Int
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- def circuitName: String
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- final val clock: Clock
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- val io: Bundle { ... /* 4 definitions in type refinement */ }
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- val maxDRAMTimingBits: Int
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- val numBankStates: Int
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- HasDRAMMASConstants
- val numRankStates: Int
- Definition Classes
- HasDRAMMASConstants
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- def portsSize: Int
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- final val reset: Reset
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- Module
- val stats: RankPowerIO
- def suggestName(seed: => String): RankPowerMonitor.this.type
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- val tREFIBits: Int
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- def override_clock: Option[Clock]
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
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(Since version Chisel 3.5) Use withClock at Module instantiation