Posted by David Biancolin
(Seaside, California) Today at FPGA2019 at 5:00 pm, I’m going to be presenting FireSim’s memory-timing model generator, FASED. FASED gives FireSim its cycle-accurate timing models for DDR3 SDRAM and last-level caches. Models are runtime-reconfigurable (that’s what those custom-runtime-configs are for), deterministic, and detailed – think of it like DRAMSim on an FPGA.
In my talk I’ll go over how the FASED instances operate, with lots of animations of token passing, and describe a number of the cool features that FASED enables. Links below!