2020

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2019

Golden Gate and Centrifuge Papers Presented at ICCAD 2019!

Posted by David Biancolin

This year at ICCAD we had two FireSim-related papers: Golden Gate and Centrifuge.

Jenny Huang presented Centrifuge, an end-to-end, HLS-based compiler framework for rapid hardware-software co-design. Using high-level synthesis, Centrifuge quickly generates a space of different RoCC accelerators. These accelerators are then integrated as verilog black-boxes in a Chipyard-based SoC, and simulated directly in FireSim. (Paper, Slides)

Later, Albert Magyar presented Golden Gate (MIDAS II), the lastest version of the FIRRTL compiler used in FireSim (included in the FireSim 1.7.0 release), Unlike MIDAS, Golden Gate can apply area-optimizations automatically, larger designs onto a single FPGA. By optimizing multi-ported memories, Golden Gate can fit 50% more BOOM cores on a single EC2 F1.2xlarge than MIDAS. (Paper, Slides)

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Tutorial on FireSim and Chipyard at MICRO 2019!

Posted by Sagar Karandikar

We’re running a hands-on tutorial on FireSim and Chipyard at the 2019 International Symposium on Microarchitecture in Columbus, OH on October 12, 2019. Learn more here: https://fires.im/micro-2019-tutorial/

Slides will be available after the tutorial, but only attendees will get to work hands-on on EC2 for free, thanks to the generosity of AWS and Xilinx. Hope to see you there!

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FireSim Selected as a IEEE Micro Top Pick of 2018!

Posted by Sagar Karandikar

The FireSim ISCA 2018 paper has been selected as an IEEE Micro Top Pick of the 2018 Computer Architecture Conferences, as one “of the papers published in 2018 that have architectural contributions of potentially high impact and significance”!

You can find a copy of our IEEE Micro Top Picks article, which summarizes our ISCA paper and provides recent project updates can be found here (for personal use). The full IEEE Micro issue with all of this year’s top picks can be found on IEEE Xplore.

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FireSim’s Memory Timing Model, FASED, to be presented at FPGA2019

Posted by David Biancolin

(Seaside, California) Today at FPGA2019 at 5:00 pm, I’m going to be presenting FireSim’s memory-timing model generator, FASED. FASED gives FireSim its cycle-accurate timing models for DDR3 SDRAM and last-level caches. Models are runtime-reconfigurable (that’s what those custom-runtime-configs are for), deterministic, and detailed – think of it like DRAMSim on an FPGA.

In my talk I’ll go over how the FASED instances operate, with lots of animations of token passing, and describe a number of the cool features that FASED enables. Links below!

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2018

Roundup of FireSim-related news from the 2018 RISC-V Summit

Posted by Sagar Karandikar

Last week at the RISC-V summit, there were lots of cool FireSim-related updates and announcements! In case you missed it, we’ve summarized them below:

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Video and Slides from FireSim Tutorial at the Chisel Community Conference 2018 now available!

Posted by Sagar Karandikar

Our slides and video from our tutorial at the 2018 Chisel Community Conference are now available!

The tutorial was broken into 5 sections, links to the video/slides are below:

Full session video:

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FireSim 1.4.0 released with new debugging tools!

Posted by Sagar Karandikar

Just in time for our tutorial at the first Chisel Community Conference, we’ve released a new version of FireSim that adds lots of new features! The headlining features with this release are new debugging tools, including assertion synthesis and Rocket Chip/BOOM commit log tracing. We’ve also bumped to more recent versions of Rocket Chip/BOOM, updated the block device model to be deterministic, started preparing infrastructure necessary to merge FireSim’s “supernode” mode to master, and done lots of other internal cleanup. See the full changelog on GitHub.

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FireSim 1.3.1 Released with support for the BOOM Out-of-Order Superscalar RISC-V Processor!

Posted by Sagar Karandikar

We’ve released a new version of FireSim that adds support for Berkeley Out-of-Order Machine (BOOM) designs as a target! BOOM is a superscalar out-of-order RISC-V implementation built at UC Berkeley by Chris Celio, which you can find more about on GitHub. We’ve successfully run SPECint 2017 with reference inputs to completion on Linux running on BOOM in FireSim on FPGAs on Amazon EC2 F1. Network support is also present, i.e. you can SSH into BOOM running on the FPGA and access the internet from within BOOM running on the FPGA.

For example, check out this GIF of a FireSim-simulated BOOM connected to the Internet and posting a tweet! The gif is real-time, not sped-up.

And the aforementioned posted tweet:

To try BOOM in FireSim on EC2 F1 with pre-built FPGA images, you can follow our Getting Started Guide/Tutorials which have been updated with notes about how to use BOOM-based designs.

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FireSim now open-sourced!

Posted by Sagar Karandikar

We’re excited to announce that FireSim is now open-source! FireSim enables cycle-accurate FPGA-accelerated simulation of Rocket Chip-based systems on Amazon EC2 F1 at 10s to 100s of MHz depending on simulation scale (e.g. ~150 MHz for a single quad-core Rocket Chip, ~10 MHz for a 1024-node, 4096-core networked datacenter of Rocket Chips with an aggregate of 16 TB of memory).

You can find the FireSim release here: github.com/firesim/firesim.

We’ve written extensive documentation, which you can find here: docs.fires.im.

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FireSim accepted to ISCA 2018!

Posted by Sagar Karandikar

FireSim has been accepted to ISCA 2018!

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, and Krste Asanović. FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. To appear, In proceedings of the 45th International Symposium on Computer Architecture (ISCA’18), Los Angeles, CA, June 2018.

Stay tuned for the paper! Check out the full program here.

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2017

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