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Roundup of FireSim-related news from the 2018 RISC-V Summit
Posted by Sagar Karandikar
Last week at the RISC-V summit, there were lots of cool FireSim-related updates and announcements! In case you missed it, we’ve summarized them below:
- The Hwacha project open-sourced their codebase and released images on FireSim.
- Esperanto Technologies announced that they used FireSim as part of their pre-silicon debug flow for their ET-Maxion Core. More here.
- The Keystone Enclave project open-sourced their codebase and released instructions to run on FireSim.
- We ran a FireSim tutorial on the first day of the summit with great attendance! Stay tuned for the full video/slides from the tutorial.
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Video and Slides from FireSim Tutorial at the Chisel Community Conference 2018 now available!
Posted by Sagar Karandikar
Our slides and video from our tutorial at the 2018 Chisel Community Conference are now available!
The tutorial was broken into 5 sections, links to the video/slides are below:
- Introduction: Slides PDF | Jump to section in video
- Building and Deploying Simulations: Slides PDF | Jump to section in video
- Simulating Custom Designs: Slides PDF | Jump to section in video
- Debugging in FireSim: Slides PDF | Jump to section in video
- Project Management/Contributing/Conclusion: Slides PDF | Video unavailable
Full session video:
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FireSim 1.4.0 released with new debugging tools!
Posted by Sagar Karandikar
Just in time for our tutorial at the first Chisel Community Conference, we’ve released a new version of FireSim that adds lots of new features! The headlining features with this release are new debugging tools, including assertion synthesis and Rocket Chip/BOOM commit log tracing. We’ve also bumped to more recent versions of Rocket Chip/BOOM, updated the block device model to be deterministic, started preparing infrastructure necessary to merge FireSim’s “supernode” mode to master, and done lots of other internal cleanup. See the full changelog on GitHub.
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FireSim 1.3.1 Released with support for the BOOM Out-of-Order Superscalar RISC-V Processor!
Posted by Sagar Karandikar
We’ve released a new version of FireSim that adds support for Berkeley Out-of-Order Machine (BOOM) designs as a target! BOOM is a superscalar out-of-order RISC-V implementation built at UC Berkeley by Chris Celio, which you can find more about on GitHub. We’ve successfully run SPECint 2017 with reference inputs to completion on Linux running on BOOM in FireSim on FPGAs on Amazon EC2 F1. Network support is also present, i.e. you can SSH into BOOM running on the FPGA and access the internet from within BOOM running on the FPGA.
For example, check out this GIF of a FireSim-simulated BOOM connected to the Internet and posting a tweet! The gif is real-time, not sped-up.
Here's the GIF of @boom_cpu posting a Tweet in FireSim! pic.twitter.com/2vhZAQcSHw
— FireSim (@firesimproject) August 19, 2018
And the aforementioned posted tweet:
This tweet was posted from a @boom_cpu in FireSim, connected to the Internet! Proof GIF coming soon!
— FireSim (@firesimproject) August 19, 2018
To try BOOM in FireSim on EC2 F1 with pre-built FPGA images, you can follow our Getting Started Guide/Tutorials which have been updated with notes about how to use BOOM-based designs.