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Golden Gate and Centrifuge Papers Presented at ICCAD 2019!
Posted by David Biancolin
This year at ICCAD we had two FireSim-related papers: Golden Gate and Centrifuge.
Jenny Huang presented Centrifuge, an end-to-end, HLS-based compiler framework for rapid hardware-software co-design. Using high-level synthesis, Centrifuge quickly generates a space of different RoCC accelerators. These accelerators are then integrated as verilog black-boxes in a Chipyard-based SoC, and simulated directly in FireSim. (Paper, Slides)
Later, Albert Magyar presented Golden Gate (MIDAS II), the lastest version of the FIRRTL compiler used in FireSim (included in the FireSim 1.7.0 release), Unlike MIDAS, Golden Gate can apply area-optimizations automatically, larger designs onto a single FPGA. By optimizing multi-ported memories, Golden Gate can fit 50% more BOOM cores on a single EC2 F1.2xlarge than MIDAS. (Paper, Slides)
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Tutorial on FireSim and Chipyard at MICRO 2019!
Posted by Sagar Karandikar
We’re running a hands-on tutorial on FireSim and Chipyard at the 2019 International Symposium on Microarchitecture in Columbus, OH on October 12, 2019. Learn more here: https://fires.im/micro-2019-tutorial/
Slides will be available after the tutorial, but only attendees will get to work hands-on on EC2 for free, thanks to the generosity of AWS and Xilinx. Hope to see you there!
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FireSim Selected as a IEEE Micro Top Pick of 2018!
Posted by Sagar Karandikar
The FireSim ISCA 2018 paper has been selected as an IEEE Micro Top Pick of the 2018 Computer Architecture Conferences, as one “of the papers published in 2018 that have architectural contributions of potentially high impact and significance”!
You can find a copy of our IEEE Micro Top Picks article, which summarizes our ISCA paper and provides recent project updates can be found here (for personal use). The full IEEE Micro issue with all of this year’s top picks can be found on IEEE Xplore.
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FireSim’s Memory Timing Model, FASED, to be presented at FPGA2019
Posted by David Biancolin
(Seaside, California) Today at FPGA2019 at 5:00 pm, I’m going to be presenting FireSim’s memory-timing model generator, FASED. FASED gives FireSim its cycle-accurate timing models for DDR3 SDRAM and last-level caches. Models are runtime-reconfigurable (that’s what those custom-runtime-configs are for), deterministic, and detailed – think of it like DRAMSim on an FPGA.
In my talk I’ll go over how the FASED instances operate, with lots of animations of token passing, and describe a number of the cool features that FASED enables. Links below!