Contents:

FireSim Papers

These are papers about FireSim and its internal components/features.

ISCA 2018: FireSim: FPGA-Accelerated, Cycle-Accurate Scale-Out System Simulation in the Public Cloud

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, and Krste Asanović. “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”. In proceedings of the 45th ACM/IEEE International Symposium on Computer Architecture (ISCA’18), Los Angeles, CA, June 2018.
Selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2018”. (link)
Selected as the Communications of the ACM Research Highlights Nominee from ISCA 2018. (link)
Paper PDF | Slides PDF | IEEE Xplore | BibTeX

FPL 2018: DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles

Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, and Krste Asanović. “DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles”. In proceedings of the 28th International Conference on Field Programmable Logic & Applications (FPL 2018), Dublin, Ireland, August 2018.
Paper PDF

FPGA 2019: FASED: FPGA-Accelerated Simulation and Evaluation of DRAM

David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanović. “FASED: FPGA-Accelerated Simulation and Evaluation of DRAM”. In proceedings of the 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, February 2019.
Paper PDF | Slides PPTX

IEEE Micro Top Picks 2018: FireSim: FPGA-Accelerated, Cycle-Accurate Scale-Out System Simulation in the Public Cloud

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, and Krste Asanović. “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”. IEEE Micro, vol. 39, no. 3, pp. 56-65, (Micro Top Picks 2018 Issue). May-June 2019.
Article PDF | IEEE Xplore | Micro Top Picks 2018 Introduction

ICCAD 2019: Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration

Qijing Huang, Christopher Yarp, Sagar Karandikar, Nathan Pemberton, Benjamin Brock, Liang Ma, Guohao Dai, Robert Quitt, Krste Asanović, and John Wawrzynek. “Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration”. In proceedings of the 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, November 2019.
Paper PDF | Slides PDF

ICCAD 2019: Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes

Albert Magyar, David T. Biancolin, Jack Koenig, Sanjit Seshia, Jonathan Bachrach, Krste Asanović, “Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes”. In proceedings of the 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, November 2019.
Paper PDF | Slides PDF

ASPLOS 2020: FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design

Sagar Karandikar, Albert Ou, Alon Amid, Howard Mao, Randy Katz, Borivoje Nikolić, and Krste Asanović, “FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design”, In Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2020), Lausanne, Switzerland, March 2020.
Paper PDF, ACM DL (open-access) | ACM DL | Pre-print PDF | Talk Video on YouTube | Open-source Docs

User Papers

These are papers that use FireSim in their work (that we know of). Send us an email if you would like your paper listed here.

ISCA 2018: A Hardware Accelerator for Tracing Garbage Collection

Martin Maas (UC Berkeley), Krste Asanović (UC Berkeley), John Kubiatowicz (UC Berkeley). “A Hardware Accelerator for Tracing Garbage Collection”. In proceedings of the 45th ACM/IEEE International Symposium on Computer Architecture (ISCA’18), Los Angeles, CA, June 2018.
Selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2018”.
Paper PDF

MICRO 2018: Composable Building Blocks to Open up Processor Design

Sizhuo Zhang (MIT), Andrew Wright (MIT), Thomas Bourgeat (MIT), Arvind (MIT). “Composable Building Blocks to Open up Processor Design”. In proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’18), Fukuoka, Japan, October 2018.
Paper PDF

EMC^2 Workshop at HPCA 2019: Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim

Farzad Farshchi (University of Kansas), Qijing Huang (UC Berkeley) and Heechul Yun (University of Kansas). “Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim”. In proccedings of The 2nd Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications, at HPCA 2019, Washington D.C., February 2019.
Paper PDF | Slides PDF

CARRV 2019 Workshop at ISCA 2019: Replicating and Mitigating Spectre Attacks on a Open Source RISC-V Microarchitecture

Abraham Gonzalez, Ben Korpan, Jerry Zhao, Ed Younis and Krste Asanović. “Replicating and Mitigating Spectre Attacks on a Open Source RISC-V Microarchitecture”. In proceedings of the Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019), at ISCA 2019, Phoenix, AZ, June 2019.
Paper PDF

CARRV 2019 Workshop at ISCA 2019: Nested-Parallelism PageRank on RISC-V Vector Multi-Processors

Alon Amid, Albert Ou, Krste Asanović and Borivoje Nikolić. “Nested-Parallelism PageRank on RISC-V Vector Multi-Processors”. In proceedings of the Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019), at ISCA 2019, Phoenix, AZ, June 2019.
Paper PDF | Slides PDF

EuroSys 2020: Keystone: An Open Framework for Architecting TEEs

Dayeol Lee, David Kohlbrenner, Shweta Shinde, Dawn Song, Krste Asanović. “Keystone: An Open Framework for Architecting TEEs”. To appear, In proceedings of the 15th European Conference on Computer Systems (EuroSys 2020), Heraklion, Greece, April 2020.
Paper PDF

Press/Blogs

NVIDIA Developer Blog: NVDLA Deep Learning Inference Compiler is Now Open Source

Rekha Mukund, Prashant Gaikwad and Mitch Harwell. NVDLA Deep Learning Inference Compiler is Now Open Source. NVIDIA Developer Blog. September 2019.
Link | NVDLA + Deep Learning Inference Compiler on FireSim, GitHub Repo

AWS Compute Blog: Bringing Datacenter-Scale Hardware-Software Co-design to the Cloud with FireSim and Amazon EC2 F1 Instances

Sagar Karandikar, Krste Asanović. Bringing Datacenter-Scale Hardware-Software Co-design to the Cloud with FireSim and Amazon EC2 F1 Instances. AWS Compute Blog. October 2017.

Link | Demo

External Talks

CARRV 2019: Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research

Speaker: Sagar Karandikar. Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research. Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019), Phoenix, AZ, June 2019.

Latch-Up 2019: FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud

Speakers: David Biancolin, Alon Amid. FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud. Latch-Up Conference 2019, Portland, OR, May 2019.

FPGA 2019: FASED: FPGA-Accelerated Simulation and Evaluation of DRAM

Speaker: David Biancolin. FASED: FPGA-Accelerated Simulation and Evaluation of DRAM. 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, February 2019.

4th Workshop on Open Source Supercomputing (OpenSuCo 4) at Supercomputing 2018: FireSim: Scalable FPGA-accelerated Cycle-Accurate Hardware Simulation in the Cloud

Speaker: Sagar Karandikar. FireSim: Scalable FPGA-accelerated Cycle-Accurate Hardware Simulation in the Cloud. 4th Workshop on Open Source Supercomputing (OpenSuCo 4) at Supercomputing 2018, Dallas, TX, November 2018.

2018 IBM Research Workshop on Architectures for Secure, Cognitive, and Datacenter Computing: FireSim: Scalable FPGA-accelerated Cycle-Accurate Hardware Simulation in the Cloud.

Speaker: Sagar Karandikar. FireSim: Scalable FPGA-accelerated Cycle-Accurate Hardware Simulation in the Cloud. 2018 IBM Research Workshop on Architectures for Secure, Cognitive, and Datacenter Computing, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, November 2018.

ModSim 2018: Workshop on Modeling & Simulation of Systems and Applications: FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-Accurate Hardware Simulation in the Cloud

Speaker: Sagar Karandikar. FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-Accurate Hardware Simulation in the Cloud. ModSim 2018: Workshop on Modeling & Simulation of Systems and Applications, Seattle, WA, August 2018.

USENIX Vail Computer Elements Workshop, 2018: FireSim: Enabling fast, cycle-accurate warehouse-scale architecture research with open hardware and FPGAs in the cloud

Speaker: Sagar Karandikar. FireSim: Enabling fast, cycle-accurate warehouse-scale architecture research with open hardware and FPGAs in the cloud. USENIX Vail Computer Elements Workshop, 2018, Vail, CO, June 2018.

ISCA 2018: FireSim: FPGA-Accelerated, Cycle-Accurate Scale-Out System Simulation in the Public Cloud

Speaker: Sagar Karandikar. FireSim: FPGA-Accelerated, Cycle-Accurate Scale-Out System Simulation in the Public Cloud. 45th ACM/IEEE International Symposium on Computer Architecture (ISCA’18), Los Angeles, CA, June 2018.

Slides PDF | Paper PDF

7th RISC-V Workshop: FireSim: Cycle-Accurate Rack-Scale System Simulation using FPGAs in the Public Cloud

Speaker: Sagar Karandikar. FireSim: Cycle-Accurate Rack-Scale System Simulation using FPGAs in the Public Cloud. 7th RISC-V Workshop, Milpitas, CA, November 2017.

Slides | Video