(Seaside, California) Today at FPGA2019 at 5:00 pm, I’m going to be presenting FireSim’s memory-timing model generator, FASED. FASED gives FireSim its cycle-accurate timing models for DDR3 SDRAM and last-level caches. Models are runtime-reconfigurable (that’s what those custom-runtime-configs are for), deterministic, and detailed – think of it like DRAMSim on an FPGA.

In my talk I’ll go over how the FASED instances operate, with lots of animations of token passing, and describe a number of the cool features that FASED enables. Links below!

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FireSim 1.17.0 Released with Support for Xilinx VCU118, U250, U280, and RHS Research Nitefury II On-Premises FPGAs

Posted by Sagar Karandikar

We just released FireSim 1.17.0, which adds support for several new on-premises FPGA boards, including:

All of these platforms support all FireSim features, including advanced debugging features like TracerV, Printf Synthesis, and more. FireSim’s automation is also maintained, enabling the ability to build large local clusters of FPGAs and automatically deploy simulations to them. The getting started guides for each FPGA (linked above) explain how to set up host systems of various scales, including:

  • A portable FireSim-host consisting of a laptop with a Thunderbolt-attached Nitefury II FPGA (e.g., FireStarter laptop on slide 32 here)
  • A desktop-based FireSim-host with one or a handful of FPGAs (e.g., FireStation desktop on slide 28 here)
  • A large on-premises FireSim-host cluster with many machines and many FPGAs

All of the platforms listed above are supported using XDMA-based shells. If you were previously using FireSim’s Vitis-based U250 support, we highly recommend migrating to the new XDMA-based U250 flow.

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