What is FireSim?
FireSim is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1). FireSim is actively developed in the Berkeley Architecture Research Group in the Electrical Engineering and Computer Sciences Department at the University of California, Berkeley.
This recent video from the Chisel Community Conference dives in-depth into FireSim. You can also scroll further down to read more FAQs.
What can I simulate with FireSim?
FireSim can simulate arbitrary hardware designs written in Chisel or designs that can be transformed into FIRRTL (including early work on supporting Verilog designs via Yosys’s Verilog to FIRRTL flow). With FireSim, you can write your own RTL (processors, accelerators, etc.) and run it at near-FPGA-prototype speeds on cloud FPGAs, while obtaining cycle-accurate performance results (i.e. matching what you would find if you taped-out a chip). Depending on the hardware design and the simulation scale, FireSim simulations run at 10s to 100s of MHz. You can also integrate custom software models for components that you don’t want/need to write as RTL.
FireSim was originally developed to simulate datacenters by combining open RTL for RISC-V processors with a custom cycle-accurate network simulation. By default, FireSim provides all the RTL and models necessary to cycle-exactly simulate from one to thousands of multi-core compute nodes, derived directly from silicon-proven and open target-RTL (RISC-V Rocket Chip and BOOM), with an optional cycle-accurate network simulation tying them together. FireSim also provides a Linux distribution that is compatible with the RISC-V systems it simulates and automates the process of including new workloads into this Linux distribution. These simulations run fast enough to interact with Linux on the simulated system at the command line, like a real computer. Users can even SSH into simulated systems in FireSim and access the Internet from within them.
What are some concrete use cases?
- Evaluating a custom hardware design, e.g. building a custom accelerator and running real workloads on it (e.g. “A Hardware Accelerator for Tracing Garbage Collection” from ISCA 2018 and the Hwacha project)
- Rapidly Customizing/Evaluating RISC-V cores, e.g. Rocket Chip and BOOM, provided as default designs in FireSim. For example, FireSim can run all of SPECInt2017 with reference inputs on Rocket Chip in parallel on 10 cloud-FPGAs in ~1 day. (e.g. “Composable Building Blocks to Open up Processor Design” from MICRO 2018)
- Debugging a Chisel design at FPGA-speeds (e.g. FireSim Debugging Docs and DESSERT from FPL 2018)
- Simulating thousand-node datacenter-scale systems with full control over the hardware (e.g. FireSim ISCA 2018 Paper, selected as an IEEE Micro Top Pick of 2018)
Where can I run FireSim?
FireSim runs on public cloud FPGAs on AWS EC2 F1, removing the high capex traditionally involved in large-scale FPGA-based simulation. FireSim is useful both for datacenter architecture research and for modeling or prototyping novel, single-SoC Chisel designs at 10s to 100s of MHz. By harnessing a standardized host platform and providing extensive automation/tooling, FireSim drastically simplifies the process of building and deploying large-scale FPGA-accelerated hardware simulations.
Where can I learn more about FireSim-related research?
Our ISCA 2018 paper discusses the FireSim framework from the perspective of simulating a 1024-node datacenter built from custom RTL and network models. A more concise version of this paper is also available in our IEEE Micro Top Picks 2018 article. The beginning of the YouTube video above talks about this use case in-detail. You can also check-out our 2-minute lightning talk for ISCA on YouTube and our full talk slides from ISCA. Check out the Publications page to see the growing list of projects and papers that have used or are currently using FireSim.
Getting Started with FireSim
Posted by Sagar Karandikar
The FireSim ISCA 2018 paper has been selected as an IEEE Micro Top Pick of the 2018 Computer Architecture Conferences, as one “of the papers published in 2018 that have architectural contributions of potentially high impact and significance”!
You can find a copy of our IEEE Micro Top Picks article, which summarizes our ISCA paper and provides recent project updates can be found here (for personal use). The full IEEE Micro issue with all of this year’s top picks can be found on IEEE Xplore.
Posted by David Biancolin
(Seaside, California) Today at FPGA2019 at 5:00 pm, I’m going to be presenting FireSim’s memory-timing model generator, FASED. FASED gives FireSim its cycle-accurate timing models for DDR3 SDRAM and last-level caches. Models are runtime-reconfigurable (that’s what those custom-runtime-configs are for), deterministic, and detailed – think of it like DRAMSim on an FPGA.
In my talk I’ll go over how the FASED instances operate, with lots of animations of token passing, and describe a number of the cool features that FASED enables. Links below!
Posted by Sagar Karandikar
Last week at the RISC-V summit, there were lots of cool FireSim-related updates and announcements! In case you missed it, we’ve summarized them below:
- The Hwacha project open-sourced their codebase and released images on FireSim.
- Esperanto Technologies announced that they used FireSim as part of their pre-silicon debug flow for their ET-Maxion Core. More here.
- The Keystone Enclave project open-sourced their codebase and released instructions to run on FireSim.
- We ran a FireSim tutorial on the first day of the summit with great attendance! Stay tuned for the full video/slides from the tutorial.