Type Members

1.  case class AXI4IdSpaceConstraint(idBits: Int = 4, maxFlight: Int = 8) extends Product with Serializable

   Constrains how many id bits of the host memory channel are used, as well as how many requests are issued per id.

   Constrains how many id bits of the host memory channel are used, as well as how many requests are issued per id. This generates hardware proportional to (2^idBits) * maxFlight.

   idBits

   The number of lower idBits of the host memory channel to use.

   maxFlight

   A bound on the number of requests the simulator will make per id.

2.  case class CPUManagedAXI4Params(addrBits: Int, dataBits: Int, idBits: Int, maxFlight: Option[Int] = None) extends Product with Serializable
3.  class CPUManagedStreamEngine extends StreamEngine
4.  abstract class ChannelizedWrapperIO extends Record with UnpackedWrapperConfig with TargetChannelIO

   Builds a Record of tokenized interfaces based on a set of FAMEChannelConnectionAnnotations.

   Builds a Record of tokenized interfaces based on a set of FAMEChannelConnectionAnnotations. Chisel-types are reconstructed by looking up a FIRRTL type in which can then be mapped back into a primitive chisel type.

   This is instantiated twice: 1) On the TargetBox, to build a chisel-interface that can link against the FIRRTL 2) To build the SimWrapper's IO. This has the subset of channel interfaces present on the TargetBox that are connected to bridges.

   This class includes many members that permit looking up record elements by channel type, and by channel name instead of using the underlying Chisel element name.

5.  class ClockRecord extends Record
6.  case class FPGAManagedAXI4Params(size: BigInt, dataBits: Int, idBits: Int, writeTransferSizes: TransferSizes, readTransferSizes: TransferSizes, interleavedId: Option[Int] = Some(0)) extends Product with Serializable

   Specifies the AXI4 interface for FPGA-driven DMA

   Specifies the AXI4 interface for FPGA-driven DMA

   size

   The size, in bytes, of the addressable region on the host CPU. The addressable region is assumed to span [0, size). Host-specific offsets should be handled by the FPGAShim.

   dataBits

   The width of the interface in bits.

   idBits

   The number of ID bits supported by the interface.

   writeTransferSizes

   Supported write transfer sizes in bytes

   readTransferSizes

   Supported read transfer sizes in bytes

   interleavedId

   Set to indicate DMA responses may be interleaved.

7.  class FPGAManagedStreamEngine extends StreamEngine
8.  class FPGATop extends LazyModule with HasWidgets
9.  class FPGATopImp extends LazyModuleImp
10.  class HostDecoupledIO[+T <: Data] extends Bundle
11.  case class HostMemChannelParams(size: BigInt, beatBytes: Int, idBits: Int, maxXferBytes: Int = 256) extends Product with Serializable

    Specifies the size and width of external memory ports

12.  class HostReadyValid extends Bundle
13.  case class IChannelDesc[T <: Data](name: String, reference: T, modelChannel: DecoupledIO[T], tokenGenFunc: Option[() => T] = None) extends Product with Serializable
14.  case class OChannelDesc[T <: Data](name: String, reference: T, modelChannel: DecoupledIO[T], comparisonFunc: (Data, DecoupledIO[Data]) => Bool = (a, b) => !b.fire || a.asUInt === b.bits.asUInt) extends Product with Serializable
15.  class PipeChannel[T <: Data] extends Module
16.  class PipeChannelIO[T <: Data] extends Bundle
17.  class PipeChannelUnitTest extends UnitTest
18.  class ReadyValidChannel[T <: Data] extends Module
19.  class ReadyValidChannelIO[T <: Data] extends Bundle
20.  class ReadyValidChannelUnitTest extends UnitTest
21.  class SimReadyValidIO[T <: Data] extends Bundle
22.  class SimWrapper extends Module with UnpackedWrapperConfig

    The SimWrapper is the shim between the transformed RTL and the rest of the Chisel-generated simulator collateral.

    The SimWrapper is the shim between the transformed RTL and the rest of the Chisel-generated simulator collateral. 1) It instantiates the tranformed target (now a collection of unconnected, decoupled models) 2) Generates channels to interconnect those models and bridges by analyzing FAMEChannelConnectionAnnotations. 3) Exposes ReadyValid interfaces for all channels sourced or sunk by a bridge as I/O

23.  class SimWrapperChannels extends ChannelizedWrapperIO
24.  case class SimWrapperConfig(annotations: Seq[Annotation], leafTypeMap: Map[ReferenceTarget, Port]) extends Product with Serializable

    The metadata required to generate the simulation wrapper.

    The metadata required to generate the simulation wrapper.

    annotations

    Notably FAMEChannelConnectionAnnotation, FAMEChannelFanoutAnnotation, BridgeIOAnnotations

    leafTypeMap

    Provides the means to rebuild chisel-types that can "link" against the transformed RTL (FIRRTL), and associate specific annotations with those types..

25.  class StreamAdapterIO extends Bundle
26.  case class StreamDriverParameters(name: String, bufferBaseAddress: Int, countMMIOAddress: Int, bufferCapacity: Int, bufferWidthBytes: Int) extends Product with Serializable

    A helper container to serialize per-stream constants to the header.

    A helper container to serialize per-stream constants to the header. This is currently somewhat redundant with the default header emission for widgets.

27.  abstract class StreamEngine extends Widget

    Base class for StreamEngine implementations.

    Base class for StreamEngine implementations. StreamEngines collect all streams from bridges, which drive two Vec[Decoupled[UInt]], and implement the transport using an AXI4 slave and / or AXI4 master port, which is presented by the host platform.

    Implementations that require an AXI4 subordinate set cpuManagedAXI4NodeOpt = Some(<node graph>) Implementations that require an AXI4 manager set fpgaManagedAXI4NodeOpt = Some(<node graph>)

28.  case class StreamEngineParameters(toCPUParams: Seq[StreamSourceParameters], fromCPUParams: Seq[StreamSinkParameters]) extends Product with Serializable

    A wrapper class for common arguments to all StreamEngine implementations.

29.  trait StreamParameters extends AnyRef

    Parameters that define a stream that are defined by bridges and collected by the engine.

30.  case class StreamSinkParameters(name: String, idx: Int, fpgaBufferDepth: Int, fpgaBufferWidthBytes: Int) extends StreamParameters with Product with Serializable
31.  case class StreamSourceParameters(name: String, idx: Int, fpgaBufferDepth: Int, fpgaBufferWidthBytes: Int) extends StreamParameters with Product with Serializable
32.  class StreamWidthAdapter extends Module
33.  class TargetBox extends BlackBox
34.  class TargetBoxIO extends ChannelizedWrapperIO
35.  trait TargetChannelIO extends AnyRef

    Represents the interface of the target to which bridges connect.

36.  trait UnpackedWrapperConfig extends AnyRef

    A convienence mixin that preprocesses the SimWrapperConfig

37.  class WriteMetadata extends Bundle