class FPGATopImp extends LazyModuleImp
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- final def !=(arg0: Any): Boolean
- Definition Classes
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- final def ##: Int
- Definition Classes
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- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
- Attributes
- protected
- Definition Classes
- BaseModule
- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
- Attributes
- protected
- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _compatAutoWrapPorts(): Unit
- Definition Classes
- BaseModule
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- val auto: AutoBundle
- Definition Classes
- LazyModuleImp → LazyModuleImpLike
- def circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- final val clock: Clock
- Definition Classes
- Module
- def clone(): AnyRef
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- protected[lang]
- Definition Classes
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- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
- val compileOptions: CompileOptions
- Definition Classes
- RawModule
- val confCPUManaged: Option[(Int, Int, Int)]
- val confCtrl: (Int, Int, Int)
- val confFPGAManaged: Option[(Int, Int, Int)]
- val confMem: (Int, Int, Int)
- val cpu_managed_axi4: Option[AXI4Bundle]
- val ctrl: WidgetMMIO
- val dangles: List[Dangle]
- Definition Classes
- LazyModuleImp → LazyModuleImpLike
- def desiredName: String
- Definition Classes
- LazyModuleImpLike → BaseModule
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- val fpga_managed_axi4: Option[AXI4Bundle]
- def genHeader(sb: StringBuilder, target: String)(implicit p: Parameters): StringBuilder
- def genVHeader(sb: StringBuilder)(implicit p: Parameters): Unit
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
- def getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- def hasSeed: Boolean
- Definition Classes
- HasId
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- def instantiate(): (AutoBundle, List[Dangle])
- Attributes
- protected[diplomacy]
- Definition Classes
- LazyModuleImpLike
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val mem: Vec[AXI4Bundle]
- val memParams: AXI4BundleParameters
- final lazy val name: String
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
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- @native() @IntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- implicit val p: Parameters
- Definition Classes
- LazyModuleImpLike
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- final val reset: Reset
- Definition Classes
- Module
- val sim: SimWrapper
- val simIo: SimWrapperChannels
- def suggestName(seed: => String): FPGATopImp.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- val wrapper: LazyModule
- Definition Classes
- LazyModuleImp → LazyModuleImpLike
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- def override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation