package passes
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- class AnnotationParameterizedWiringTransform[SourceType <: SingleTargetAnnotation[ReferenceTarget], SinkType <: SingleTargetAnnotation[ReferenceTarget]] extends Transform with DependencyAPIMigration
A type-parameterized wrapper for the WiringTransform that accepts a specific Source and Sink annotation pair.
A type-parameterized wrapper for the WiringTransform that accepts a specific Source and Sink annotation pair. It collects and maps these specific annotations into WiringAnnotations.
This permits sources and sinks for different features to exist without having to wire them all at once (since some passes in the compiler may inject new sinks or sources, before their opposite has been added).
- class AutoCounterTransform extends Transform with AutoCounterConsts
Take the annotated cover points and convert them to counters
- class BridgeTopWiring extends Transform
A utility transform used to implement features that are finely distributed through out the target, such as assertion and printf synthesis.
A utility transform used to implement features that are finely distributed through out the target, such as assertion and printf synthesis. This transform preforms most of the circuit modifications and analysis to emit BridgeIOAnnotations and FCCAs directly. For this pass to function correctly, the clock bridge must already be extracted.
For each BridgeTopWiringAnnotation, this transform: 1) Wires out every instance of that signal to a unique port in the top-level module These will be referenced by Bridge FCCAs and will become simulation channels. 2) Determines the source clock (these are now inputs on the top-level module) to which each that port is synchronous
For each clock that is synchronous with at least one output port: 1) Loop that clock back to a new output port (Bridge FCCAs will point at this clock)
Finally emit a BridgeTopWiringOutputAnnotation for each created data-output port.
- case class BridgeTopWiringAnnotation(target: ReferenceTarget, clock: ReferenceTarget) extends Annotation with FAMEAnnotation with DontTouchAllTargets with Product with Serializable
Provides signals for the transform to wire to the top-level of hte module hierarchy.
Provides signals for the transform to wire to the top-level of hte module hierarchy.
- target
The signal to be plumbed to the top
- clock
The clock to which this signal is sychronous. This will _not_ be wired.
- case class BridgeTopWiringOutputAnnotation(pathlessSource: ReferenceTarget, absoluteSource: ReferenceTarget, topSink: ReferenceTarget, srcClockPort: ReferenceTarget, sinkClockPort: ReferenceTarget) extends Annotation with FAMEAnnotation with Product with Serializable
Provides reference targets to the newly generated top-level IO and a generated output-clock port that output is synchronous to.
Provides reference targets to the newly generated top-level IO and a generated output-clock port that output is synchronous to.
- pathlessSource
The original target passed in a BridgeTopWiringAnnotation
- absoluteSource
An absolute reference target to the particular instance of that signal that drives the new output. NB: A single BridgeTopWiringAnnotation will generate as many output annotations as there are instances of the pathless source.
- topSink
The new top-level port the source has been connected to
- srcClockPort
The input clock associated with the source
- case class ChannelClockInfoAnnotation(infoMap: Map[String, RationalClock]) extends NoTargetAnnotation with Product with Serializable
ChannelClockInfoAnalysis's output annotation.
ChannelClockInfoAnalysis's output annotation. Maps channel global name (See FAMEChannelConnectionAnnotation to a clock info class.
- case class ClockSourceAnnotation(queryTarget: ReferenceTarget, source: Option[ReferenceTarget]) extends Annotation with Product with Serializable
- class ClockSourceFinder extends AnyRef
A utility for finding the upstream drivers of arbitrary clock signals in a circuit.
A utility for finding the upstream drivers of arbitrary clock signals in a circuit. find and return that input port.
- class EmitFirrtl extends Transform
- class EnableAndRunDedupOnce extends Transform with DependencyAPIMigration
Aggressive deduplication during phases of the Golden Gate flow where the target design is still being transformed can cause issues with bridge annotations that define connectivity.
Aggressive deduplication during phases of the Golden Gate flow where the target design is still being transformed can cause issues with bridge annotations that define connectivity. To work around this issue, the compiler relies on a global NoCircuitDedupAnnotation; however, this transform ignores the annotation to run dedup a single time after target transformation completes rather than several times as it would if enabled globally.
- case class FindClockSourceAnnotation(target: ReferenceTarget, originalTarget: Option[ReferenceTarget] = None) extends Annotation with Product with Serializable
- class FireSimPropertyLibrary extends BasePropertyLibrary
- trait FunctionalPass[T] extends AnyRef
A pass that is described as a chain of pure function calls.
A pass that is described as a chain of pure function calls.
- T
The type of the analysis object returned by the analysis phase.
- case class HostClockSink(target: ReferenceTarget) extends SingleTargetAnnotation[ReferenceTarget] with Product with Serializable
Labels sinks that must be driven by the HostClock.
- trait NoAnalysisPass extends FunctionalPass[Unit]
A pass that simply applies a (Circuit) => Circuit function.
- class RunConvertAssertsEarly extends Transform with DependencyAPIMigration
Ensure ConvertAsserts is run as early as possible
Ensure ConvertAsserts is run as early as possible
This transform does nothing but inject a dependency such that ConvertAsserts runs as early in the compiler as possible (before RemoveCHIRRTL). This permits new assertion nodes to be lowered into the old form such they can be detected by AssertionSynthesis. There is currently no simple mechanism to re-associate an assert-printf pair, without introducing new annotations.
- case class SignalInfo(decl: Statement, assigns: Statement, ref: Expression) extends Product with Serializable
A utility for keeping statements defining and connecting signals to a piece of hardware together with a reference to the component.
A utility for keeping statements defining and connecting signals to a piece of hardware together with a reference to the component. This is useful for passes that insert hardware, since the "collateral" of that object can be kept in one place.
- class SimplifyMems extends Transform
Lowers memories without splitting them, but without the complexity of ReplaceMemMacros
- class StroberMetaData extends AnyRef
- case class TargetMalformedException(message: String) extends RuntimeException with Product with Serializable
Value Members
- object AutoILATransform extends Transform with DependencyAPIMigration
Finds all FPGADebug annotations deployed throughout the circuit, and wires them to a single ILA instance at the top of the module hierarchy.
Finds all FPGADebug annotations deployed throughout the circuit, and wires them to a single ILA instance at the top of the module hierarchy. The ILA is wrapped in a shim module that preserves the marked signal names and instance path names in its port list. The shim module instantiates the Xilinx IP only when
SYNTHESIS is defined.This emits an annotation pass generates annotations for two files:
- A ip generation script (tcl) for the ILA IP
- A verilog implementation for the ILA shim. This is verbatim verilog so as to permit using verilog preprocessor macros.
Caveats:
- Targets labelled with the FPGADebug annotation must be synchronous to the simulator's host clock. In practice, the PlatformShim is the only location where it is possible to violate this assumption.
- object BridgeTopWiring
- object ChannelClockInfoAnalysis extends Transform
Returns a map from a channel's global name to a RationalClock case class which contains metadata about the target clock including its name and relative frequency to the base clock
- object ClockSourceFinder
Contains exception classes for midas.passes.ClockSourceFinder
- object CoerceAsyncToSyncReset extends Transform
Replaces all AsyncResets and Reset types with Bools (synchronous reset).
- object DefineAbstractClockGate extends Transform with FunctionalPass[CircuitName]
This pass ensures that the AbstractClockGate blackbox is defined in a circuit, so that it can later be instantiated.
This pass ensures that the AbstractClockGate blackbox is defined in a circuit, so that it can later be instantiated. The blackbox clock gate has the following signature:
module AbstractClockGate(input I, input CE, output O);
I and O are the input and output clocks, respectively, while CE is the enable signal.
- object ExpressionTransformer
Generates a function transforming a circuit from a partial function describing how each expression, if matched, is transformed.
Generates a function transforming a circuit from a partial function describing how each expression, if matched, is transformed. This is applied recursively to all expressions in the circuit.
- object FindClockSources extends Transform
- object GlobalResetConditionWiring extends AnnotationParameterizedWiringTransform[GlobalResetCondition, GlobalResetConditionSink]
- object HoistStopAndPrintfEnables extends Transform with DependencyAPIMigration
Pushes enable expressions into separate nodes that can be consistently optimized across by CSE.
Pushes enable expressions into separate nodes that can be consistently optimized across by CSE. This ensures that associated pairs of stops and printfs will have references to a common enable node, which allows AssertionSynthesis to correctly group and synthesize them.
- object HostClockWiring extends AnnotationParameterizedWiringTransform[HostClockSource, HostClockSink]
Does final host clock wiring for transform-injected hardware.
- object ModuleTransformer
Generates a function transforming a circuit from a partial function describing how each module, if matched, is transformed.
- object OrElseIdentity
Adds a default to a partial function.
- object PassThru
A utility for creating a wire that "echoes" the value of an existing expression.
- object RemoveTrivialPartialConnects extends Pass with PreservesAll[Transform]
- object ReplaceExpression
A utility for matching and replacing FIRRTL expression trees
- object StatementTransformer
Generates a function transforming a circuit from a partial function describing how each statement, if matched, is transformed.
Generates a function transforming a circuit from a partial function describing how each statement, if matched, is transformed. This is applied recursively to all statements in the circuit.
- object StroberMetaData
This file contains legacy FIRRTL features that did not exist in upstream FIRRTL at the time of Strober's development.
This file contains legacy FIRRTL features that did not exist in upstream FIRRTL at the time of Strober's development. These continue to be used in: AssertionSynthesis
- object UpdateBridgeClockInfo extends Transform
Determines which clock each bridge is synchronous with, and updates that bridge's IO annotation to include it's domain clock info.
- object Utils
- object postorder
- object preorder