class SimWrapper extends Module with UnpackedWrapperConfig
The SimWrapper is the shim between the transformed RTL and the rest of the Chisel-generated simulator collateral. 1) It instantiates the tranformed target (now a collection of unconnected, decoupled models) 2) Generates channels to interconnect those models and bridges by analyzing FAMEChannelConnectionAnnotations. 3) Exposes ReadyValid interfaces for all channels sourced or sunk by a bridge as I/O
- Self Type
- SimWrapper
Linear Supertypes
Ordering
- Alphabetic
- By Inheritance
Inherited
- SimWrapper
- UnpackedWrapperConfig
- Module
- RawModule
- BaseModule
- IsInstantiable
- HasId
- InstanceId
- AnyRef
- Any
- Hide All
- Show All
Visibility
- Public
- Protected
Instance Constructors
- new SimWrapper(config: SimWrapperConfig)(implicit p: Parameters)
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
- Attributes
- protected
- Definition Classes
- BaseModule
- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
- Attributes
- protected
- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _compatAutoWrapPorts(): Unit
- Definition Classes
- BaseModule
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def bindRVChannelDeq[T <: Data](deq: SimReadyValidIO[T], port: TargetRVPortType): Unit
- def bindRVChannelEnq[T <: Data](enq: SimReadyValidIO[T], port: TargetRVPortType): Unit
- val bridgeAnnos: ArrayBuffer[BridgeIOAnnotation]
- Definition Classes
- UnpackedWrapperConfig
- val chAnnos: ArrayBuffer[FAMEChannelConnectionAnnotation]
- Definition Classes
- UnpackedWrapperConfig
- val channelGroups: Map[String, ArrayBuffer[FAMEChannelConnectionAnnotation]]
- val channelPorts: SimWrapperChannels
- val channelToFanoutName: Map[String, String]
- def circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- final val clock: Clock
- Definition Classes
- Module
- val clockChannels: ArrayBuffer[FAMEChannelConnectionAnnotation]
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
- val compileOptions: CompileOptions
- Definition Classes
- RawModule
- val config: SimWrapperConfig
- Definition Classes
- SimWrapper → UnpackedWrapperConfig
- def desiredName: String
- Definition Classes
- BaseModule
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- val fanoutAnnos: ArrayBuffer[FAMEChannelFanoutAnnotation]
- Definition Classes
- UnpackedWrapperConfig
- def genClockChannel(chAnno: FAMEChannelConnectionAnnotation): Unit
- def genPipeChannel(chAnnos: Iterable[FAMEChannelConnectionAnnotation], primaryChannelName: String): Iterable[PipeChannel[Data]]
Implements a pipe channel.
Implements a pipe channel.
- chAnnos
A group of FAMEChannelFanoutAnnotations that have a common source. Groups with size > 1 represent a fanout connection in the source RTL. Each source token will be duplicated and enqueued into each channel.
- primaryChannelName
For fanouts that are sourced by a bridge, this provides the unique chname used to look up the bridge-side interface in channelPorts.
- def genReadyValidChannel(chAnno: FAMEChannelConnectionAnnotation): ReadyValidChannel[Data]
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
- def getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- def getPipeChannelType(chAnno: FAMEChannelConnectionAnnotation): Data
- def getReadyValidChannelType(chAnno: FAMEChannelConnectionAnnotation): Data
- def hasSeed: Boolean
- Definition Classes
- HasId
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val isSecondaryFanout: Set[String]
- val leafTypeMap: Map[ReferenceTarget, Port]
- Definition Classes
- UnpackedWrapperConfig
- final lazy val name: String
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- val outerConfig: SimWrapperConfig
- implicit val p: Parameters
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- val pipeChannelFCCAs: ArrayBuffer[FAMEChannelConnectionAnnotation]
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- final val reset: Reset
- Definition Classes
- Module
- val rvChannels: ArrayBuffer[ReadyValidChannel[Data]]
- def suggestName(seed: => String): SimWrapper.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- val target: TargetBox
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- def override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation