case class FPGAManagedAXI4Params(size: BigInt, dataBits: Int, idBits: Int, writeTransferSizes: TransferSizes, readTransferSizes: TransferSizes, interleavedId: Option[Int] = Some(0)) extends Product with Serializable
Specifies the AXI4 interface for FPGA-driven DMA
- size
The size, in bytes, of the addressable region on the host CPU. The addressable region is assumed to span [0, size). Host-specific offsets should be handled by the FPGAShim.
- dataBits
The width of the interface in bits.
- idBits
The number of ID bits supported by the interface.
- writeTransferSizes
Supported write transfer sizes in bytes
- readTransferSizes
Supported read transfer sizes in bytes
- interleavedId
Set to indicate DMA responses may be interleaved.
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- new FPGAManagedAXI4Params(size: BigInt, dataBits: Int, idBits: Int, writeTransferSizes: TransferSizes, readTransferSizes: TransferSizes, interleavedId: Option[Int] = Some(0))
- size
The size, in bytes, of the addressable region on the host CPU. The addressable region is assumed to span [0, size). Host-specific offsets should be handled by the FPGAShim.
- dataBits
The width of the interface in bits.
- idBits
The number of ID bits supported by the interface.
- writeTransferSizes
Supported write transfer sizes in bytes
- readTransferSizes
Supported read transfer sizes in bytes
- interleavedId
Set to indicate DMA responses may be interleaved.
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- final def !=(arg0: Any): Boolean
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- def axi4BundleParams: AXI4BundleParameters
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- val dataBits: Int
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- val idBits: Int
- val interleavedId: Option[Int]
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- val readTransferSizes: TransferSizes
- val size: BigInt
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- val writeTransferSizes: TransferSizes