object SimUtils
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Type Members
- type ChTuple = (Bits, String)
- type ParsePortsTuple = (List[ChTuple], List[ChTuple], List[RVChTuple], List[RVChTuple])
- trait PortTuple[T] extends AnyRef
- type RVChTuple = (ReadyValidIO[Data], String)
- case class TargetRVPortTuple(source: Option[TargetRVPortType], sink: Option[TargetRVPortType]) extends PortTuple[TargetRVPortType] with Product with Serializable
- type TargetRVPortType = (ReadyValidIO[ValidIO[Data]], ReadyValidIO[Bool])
- case class WirePortTuple(source: Option[ReadyValidIO[Data]], sink: Option[ReadyValidIO[Data]]) extends PortTuple[ReadyValidIO[Data]] with Product with Serializable
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- def buildChannelType(portTypeMap: Map[ReferenceTarget, Port], refTargets: Seq[ReferenceTarget]): Data
Construct a type for a channel carrying the wires referenced by the list of targets.
Construct a type for a channel carrying the wires referenced by the list of targets.
The reference targets denote the set of fields of a port which should be included in a channel. A type is built including only those fields, which should be unidirectional. This is now used to remove the valid field of a ready-valid channel payload. The "bits_" suffix of fields is removed to improve readability, but this should be changed in the future.
- portTypeMap
Mapping from port references to their types.
- refTargets
List of fields in the channel. Must all point to sub-fields or sub-indices of the port.
- def clone(): AnyRef
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- def lowerAggregateIntoLeafTargets(bits: Data): Seq[ReferenceTarget]
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- def parsePorts(io: Data, prefix: String = "", alsoFlattenRVPorts: Boolean = true): ParsePortsTuple
- def parsePorts(io: Seq[(String, Data)], alsoFlattenRVPorts: Boolean): ParsePortsTuple
- def parsePortsSeq(io: Seq[(String, Data)], alsoFlattenRVPorts: Boolean = true): ParsePortsTuple
- def prefixWith(prefix: String, base: Any): String
- def rvChannelNamePair(tuple: RVChTuple): (String, String)
- def rvChannelNamePair(chName: String): (String, String)
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