Type Members

1.  class AXI4AddressTranslation extends LazyModule
2.  class AXI4TieOff extends LazyModule

   Ties off an AXI4 edge by spoofing a master that drives no requests.

3.  class AssertBridgeModule extends BridgeModule[HostPortIO[AssertBridgeRecord]]
4.  case class AssertBridgeParameters(assertPortName: String, resetPortName: String, assertMessages: Seq[String]) extends Product with Serializable
5.  class AssertBridgeRecord extends Record
6.  class AutoCounterBridgeModule extends BridgeModule[HostPortIO[AutoCounterBundle]] with AutoCounterConsts
7.  class AutoCounterBundle extends Record
8.  trait AutoCounterConsts extends AnyRef
9.  case class AutoCounterParameters(eventMetadata: Seq[EventMetadata], triggerName: String, resetPortName: String) extends Product with Serializable
10.  class BRAMFlowQueue[T <: Data] extends Module
11.  class BRAMQueue[T <: Data] extends Module
12.  trait Bridge[HPType <: Record with HasChannels, WidgetType <: BridgeModule[HPType]] extends AnyRef
13.  case class BridgeAnnotation(target: ModuleTarget, bridgeChannels: Seq[BridgeChannel], widgetClass: String, widgetConstructorKey: Option[_ <: AnyRef]) extends SingleTargetAnnotation[ModuleTarget] with FAMEAnnotation with HasSerializationHints with Product with Serializable

    A serializable annotation emitted by Chisel Modules that extend Bridge

    A serializable annotation emitted by Chisel Modules that extend Bridge

    target

    The module representing an Bridge. Typically a black box

    bridgeChannels

    A list of descriptors for the channels attached to the bridge. FCCAs are materialized from these descriptors.

    widgetClass

    The full class name of the BridgeModule generator

    widgetConstructorKey

    A optional, serializable object which will be passed to the constructor of the BridgeModule. Consult https://github.com/json4s/json4s#serialization to better understand what can and cannot be serialized. To provide additional typeHints to the serilization/deserialization protocol mix in HasSerializationHints into your ConstructorKey's class and return additional pertinent classes

14.  sealed trait BridgeChannel extends AnyRef
15.  abstract class BridgeModule[HostPortType <: Record with HasChannels] extends Widget
16.  abstract class BridgeModuleImp[HostPortType <: Record with HasChannels] extends WidgetImp
17.  sealed trait CPPLiteral extends AnyRef
18.  class CRIO extends Bundle
19.  case class CStrLit(value: String) extends CPPLiteral with Product with Serializable
20.  trait ChannelizedHostPortIO extends HasChannels

    A host-side bridge interface trait that permits finer-grained control over channel definition versus HostPortIO.

    A host-side bridge interface trait that permits finer-grained control over channel definition versus HostPortIO. Required for describing bridges that are combinationally coupled to the target.

21.  case class ClockBridgeChannel(name: String, sinks: Seq[ReferenceTarget], clocks: Seq[RationalClock], clockMFMRs: Seq[Int]) extends BridgeChannel with Product with Serializable

    Descriptor for a clock channel originating from a clock bridge.

22.  sealed trait ClockBridgeConsts extends AnyRef
23.  class ClockBridgeModule extends BridgeModule[ClockTokenVector]

    The host-side implementation.

    The host-side implementation. Based on provided a clock information, generates a clock token stream which will be sunk by the FAME-1 hub model. This token stream does not depend on the runtime-behavior of the target, allowing this bridge run ahead of the rest of the simulation.

    Target and host time measurements provided by simif_t are facilitated with MMIO to this bridge

24.  case class ClockParameters(clocks: Seq[RationalClock]) extends Product with Serializable

    Parameters to construct a clock bridge from.

    Parameters to construct a clock bridge from. Aggregates information about all the output clocks.

    clocks

    Clock information for each output clock.

25.  class ClockTokenVector extends Bundle with HasChannels with ClockBridgeConsts

    The host-land clock bridge interface.

    The host-land clock bridge interface. This consists of a single channel, carrying clock tokens. A clock token is a Vec[Bool], one element per clock, When a bit is set, that clock domain will fire in the simulator time step that consumes this clock token.

    NB: The target-time elapsed between tokens is not necessarily constant.

26.  case class CppBoolean(value: Boolean) extends CPPLiteral with Product with Serializable
27.  case class CppStruct(name: String, fields: Seq[(String, CPPLiteral)]) extends CPPLiteral with Product with Serializable
28.  class DecoupledCRIO[+T <: Data] extends DecoupledIO[T]
29.  case class DecoupledSinkEntry(node: DecoupledIO[UInt], name: String, substruct: Boolean) extends MCRMapEntry with Product with Serializable
30.  case class DecoupledSourceEntry(node: DecoupledIO[UInt], name: String, substruct: Boolean) extends MCRMapEntry with Product with Serializable
31.  case class EventMetadata(portName: String, label: String, description: String, width: Int, opType: PerfCounterOpType) extends AutoCounterConsts with Product with Serializable

    Captures target-side information about an annotated event

    Captures target-side information about an annotated event

    portName

    the name of the IF exposed to the bridge by the autocounter transform

    label

    The user provided AutoCounterFirrtlAnnotation.label prepended with an instance path.

    description

    A passthrough of AutoCounterFirrtlAnnotation.description

    width

    The bitwidth of the event

    opType

    The type of accumulation operation to apply to event

32.  class FuzzingUIntSourceBridge extends BlackBox with Bridge[HostPortIO[FuzzingUIntSourceTargetIO], FuzzingUIntSourceBridgeModule]
33.  class FuzzingUIntSourceBridgeModule extends BridgeModule[HostPortIO[FuzzingUIntSourceTargetIO]]
34.  case class FuzzingUIntSourceKey(width: Int) extends Product with Serializable
35.  class FuzzingUIntSourceTargetIO extends Bundle
36.  trait HasChannels extends AnyRef
37.  trait HasWidgets extends AnyRef
38.  trait HostDramHeaderConsts extends AnyRef

    A common trait for referring collateral in the generated header.

39.  class HostPortIO[+T <: Data] extends Record with HasChannels
40.  class IdentityModule[T <: Data] extends Module
41.  case class Int64(value: BigInt) extends IntLikeLiteral with Product with Serializable
42.  sealed trait IntLikeLiteral extends CPPLiteral
43.  class LoadMemIO extends WidgetIO
44.  class LoadMemWidget extends Widget
45.  class LoadMemWriteRequest extends NastiBundle
46.  class LoadMemWriter extends NastiModule
47.  class MCRFile extends NastiModule
48.  class MCRFileMap extends AnyRef

    Manages the metadata associated with a widget's configuration registers (exposed via the control bus).

    Manages the metadata associated with a widget's configuration registers (exposed via the control bus). Registers are incrementally allocated, which each register consuming a fixed number of bytes of the address space.

    This derives from a very early form of CSR handling in Rocket Chip which has since been replaced with diplomacy and its regmapper utilities.

49.  class MCRIO extends NastiBundle
50.  abstract class MCRMapEntry extends AnyRef
51.  case class MemorySlaveConstraints(address: Seq[AddressSet], supportsRead: TransferSizes, supportsWrite: TransferSizes) extends Product with Serializable

    Constrains the "virtual" memory region as seen by Bridge.

    Constrains the "virtual" memory region as seen by Bridge.

    address

    AddressSets defining the addresses the bridge will access. These addresses may overlap with other bridges, Golden Gate will ensure isolation by using a base-and-bound scheme based on the range of the requested addresses. THe reqested addresses need not be contiguous and their union need not being at address 0. Currently non-contiguous regions will be allocated memory as though it were continguous.

    supportsRead

    TransferSize specifying the range of read transaction sizes this bridge will produce

    supportsWrite

    TransferSize specifying the range of write transaction sizes this bridge will produce Example. Request 4GiB of host DRAM, with read and write transactions that range between 1 and 64B: MemorySlaveConstraints(AddressSet(0, 0x3FFF_FFFF), TransferSizes(1, 64), TransferSizes(1, 64)) Q: Perhaps the last two parameters should be removed, and the bridge should be forced to work the slaves it is given?

52.  class MultiQueue[T <: Data] extends Module

    An extension of queue that co locates a set of Queues at a single mem.

    An extension of queue that co locates a set of Queues at a single mem. Key assumptions: 1) A writer to a queue dumps a complete transaction into a single queue before it proceeds to enq to another queue. 2) A reader consumes the contents of a queue entirely before reading from another This way we require only a single set of read and write pointers

53.  class MultiQueueIO[T <: Data] extends QueueIO[T]
54.  class PeekPokeBridge extends BlackBox with Bridge[PeekPokeTokenizedIO, PeekPokeBridgeModule]
55.  class PeekPokeBridgeModule extends BridgeModule[PeekPokeTokenizedIO]
56.  case class PeekPokeKey(peeks: Seq[SerializableField], pokes: Seq[SerializableField], maxChannelDecoupling: Int = 2) extends Product with Serializable
57.  class PeekPokeTargetIO extends Record
58.  class PeekPokeTokenizedIO extends Record with ChannelizedHostPortIO
59.  class PeekPokeWidgetIO extends WidgetIO
60.  case class Permissions(readable: Boolean, writeable: Boolean) extends Product with Serializable
61.  case class PipeBridgeChannel(name: String, clock: ReferenceTarget, sinks: Seq[ReferenceTarget], sources: Seq[ReferenceTarget], latency: Int) extends BridgeChannel with Product with Serializable

    Descriptor for a pipe channel ending at the bridge.

62.  case class PipeChannelMetadata(field: Data, clock: Clock, bridgeSunk: Boolean, latency: Int = 0) extends Product with Serializable

    A utility trait for translating chisel references into unidirected FCCAs This becomes more useful when there are channel types.

63.  class PlusArgsBridge extends BlackBox with Bridge[PlusArgsBridgeHostIO, PlusArgsBridgeModule]

    The target-side of the PlusArg bridge.

64.  class PlusArgsBridgeHostIO extends Bundle with ChannelizedHostPortIO

    The host-side interface.

    The host-side interface. This bridge has single channel with the PlusArg value.

65.  class PlusArgsBridgeModule extends BridgeModule[PlusArgsBridgeHostIO]

    The host-side implementation.

    The host-side implementation. Calculates widths and bundles multiple 32 bit MMIO to the exact width of params.width. If params.width does not evenly divide by 32 a MMIO with the remainder bits will be created. The remainders name will always be outN where N is the last MMIO

    initDone is used as valid for the outChannel. The C++ driver ensures that all outN are driven before initDone is asserted

66.  case class PlusArgsBridgeParams(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32) extends Product with Serializable

    Defines a PlusArgs interface.

    Defines a PlusArgs interface. The signature here was copied from rocket-chip/src/main/scala/util/PlusArg.scala

    name

    string identifier, should include "name=%d"

    default

    The value of the register if no matching PlusArg is provided

    docstring

    The doctring

    width

    The width of the register, in bits

67.  class PlusArgsBridgeTargetIO extends Bundle

    The target IO.

    The target IO. This drives the value (default, or overriden) that comes out of the PlusArgs bridge

68.  class PrintBridgeModule extends BridgeModule[HostPortIO[PrintRecordBag]] with StreamToHostCPU
69.  case class PrintBridgeParameters(resetPortName: String, printPorts: Seq[PrintPort]) extends Product with Serializable
70.  case class PrintPort(name: String, ports: Seq[(String, String)], format: String) extends Product with Serializable
71.  class PrintRecord extends Record
72.  class PrintRecordBag extends Record
73.  case class RationalClock(name: String, multiplier: Int, divisor: Int) extends Product with Serializable

    Defines a generated clock as a rational multiple of some reference clock.

    Defines a generated clock as a rational multiple of some reference clock. The generated clock has a frequency (multiplier / divisor) times that of reference.

    name

    An identifier for the associated clock domain

    multiplier

    See class comment.

    divisor

    See class comment.

74.  class RationalClockBridge extends BlackBox with ClockBridgeConsts

    The default target-side clock bridge.

    The default target-side clock bridge. Generates a vector of clocks rationally related to one another. At least one clock must have it's ratio set to one, this will be used as the base clock of the system. Global simulation times, for features that might span multiple clock domains like printf synthesis, are expressed in terms of this base clock.

75.  case class ReadyValidBridgeChannel(fwdName: String, revName: String, clock: ReferenceTarget, sinks: Seq[ReferenceTarget], sources: Seq[ReferenceTarget], valid: ReferenceTarget, ready: ReferenceTarget) extends BridgeChannel with Product with Serializable

    Descriptor for a Ready-Valid channel originating from a bridge.

76.  case class RegisterEntry(node: Data, name: String, permissions: Permissions, substruct: Boolean) extends MCRMapEntry with Product with Serializable
77.  class ResetPulseBridge extends BlackBox with Bridge[ResetPulseBridgeHostIO, ResetPulseBridgeModule]
78.  class ResetPulseBridgeHostIO extends Bundle with ChannelizedHostPortIO

    The host-side interface.

    The host-side interface. This bridge has single channel with a bool payload. ChannelizedHostPortIO.OutputChannel associates the reset on the target side IF with a channel named reset on the host-side BridgeModule (determined by reflection, since we're extending Bundle).

79.  class ResetPulseBridgeModule extends BridgeModule[ResetPulseBridgeHostIO]
80.  case class ResetPulseBridgeParameters(activeHigh: Boolean = true, defaultPulseLength: Int = 50, maxPulseLength: Int = 1023) extends Product with Serializable

    The ResetPulseBridge drives a bool pulse from time zero for a runtime-configurable number of cycles.

    The ResetPulseBridge drives a bool pulse from time zero for a runtime-configurable number of cycles. These are its elaboration-time parameters.

    activeHigh

    When true, reset is initially set at time 0.

    defaultPulseLength

    The number of cycles the reset is held at the time 0 value.

    maxPulseLength

    The maximum runtime-configurable pulse length that the bridge will support.

81.  class ResetPulseBridgeTargetIO extends Bundle
82.  class SatUpDownCounter extends Module

    A saturating up down counter.

83.  class SatUpDownCounterIO extends Bundle
84.  class SimulationMaster extends Widget
85.  class SimulationMasterIO extends WidgetIO
86.  case class StdMap(typeName: String, fields: Seq[(String, CPPLiteral)]) extends CPPLiteral with Product with Serializable
87.  case class StdVector(typeName: String, elems: Seq[CPPLiteral]) extends CPPLiteral with Product with Serializable
88.  trait StreamFromHostCPU extends AnyRef

    Adds a stream interface that will be dequeued from by the BridgeModule.

89.  trait StreamToHostCPU extends AnyRef

    Adds a stream interface that will be enqueued to by the BridgeModule.

90.  class TerminationBridge extends BlackBox with Bridge[TerminationBridgeHostIO, TerminationBridgeModule]
91.  class TerminationBridgeHostIO extends Bundle with ChannelizedHostPortIO
92.  class TerminationBridgeModule extends BridgeModule[TerminationBridgeHostIO]
93.  case class TerminationBridgeParams(conditionInfo: Seq[TerminationCondition]) extends Product with Serializable

    A seq of termination conditions one for each concurrently running program

94.  class TerminationBridgeTargetIO extends Bundle
95.  case class TerminationCondition(isErr: Boolean, message: String) extends Product with Serializable

    Defines a condition under which the simulator should halt.

96.  case class UInt32(value: BigInt) extends IntLikeLiteral with Product with Serializable
97.  case class UInt64(value: BigInt) extends IntLikeLiteral with Product with Serializable
98.  trait UsesHostDRAM extends HostDramHeaderConsts

    A BridgeModule mixin indicating it wishes to be allocated FPGA DRAM.

99.  case class Verbatim(name: String) extends CPPLiteral with Product with Serializable
100.  abstract class Widget extends LazyModule
101.  class WidgetIO extends ParameterizedBundle
102.  abstract class WidgetImp extends LazyModuleImp
103.  class WidgetMMIO extends NastiIO with HasNastiParameters