class BRAMFlowQueue[T <: Data] extends Module
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- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
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- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
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- val atLeastTwo: Bool
- def circuitName: String
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- final val clock: Clock
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- val compileOptions: CompileOptions
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- val deq_done: Bool
- val deq_ptr: UInt
- def desiredName: String
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- val do_deq: Bool
- val do_enq: Bool
- val do_flow: Bool
- val empty: Bool
- val enq_ptr: UInt
- val entries: Int
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- def getCommands: Seq[Command]
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- def getModulePorts: Seq[Data]
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- val io: QueueIO[T]
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- final lazy val name: String
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- def portsSize: Int
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- val ptr_match: Bool
- val raddr: UInt
- val ram: Mem[T]
- val ram_out_valid: Bool
- val ren: Bool
- final val reset: Reset
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- def suggestName(seed: => String): BRAMFlowQueue.this.type
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- final def synchronized[T0](arg0: => T0): T0
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- def override_clock: Option[Clock]
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
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- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation