class MultiQueue[T <: Data] extends Module
An extension of queue that co locates a set of Queues at a single mem. Key assumptions: 1) A writer to a queue dumps a complete transaction into a single queue before it proceeds to enq to another queue. 2) A reader consumes the contents of a queue entirely before reading from another This way we require only a single set of read and write pointers
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- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
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- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
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- val compileOptions: CompileOptions
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- val deqAddrReg: UInt
- val deqPtr: UInt
- val deqPtrs: Vec[UInt]
- val deqValid: Bool
- def desiredName: String
- Definition Classes
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- val do_deq: Bool
- val do_enq: Bool
- val empty: Bool
- val enqPtrs: Vec[UInt]
- val entries: Int
- final def eq(arg0: AnyRef): Boolean
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- def equals(that: Any): Boolean
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- val full: Bool
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- def getCommands: Seq[Command]
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- def getModulePorts: Seq[Data]
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- def hashCode(): Int
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- def instanceName: String
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- val io: MultiQueueIO[T]
- final def isInstanceOf[T0]: Boolean
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- val maybe_full: Vec[Bool]
- final lazy val name: String
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- final def ne(arg0: AnyRef): Boolean
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- val numQueues: Int
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- def portsContains(elem: Data): Boolean
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- def portsSize: Int
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- val ptr_matches: Vec[Bool]
- val ram: SyncReadMem[T]
- final val reset: Reset
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- def suggestName(seed: => String): MultiQueue.this.type
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- final def wait(arg0: Long, arg1: Int): Unit
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- def override_clock: Option[Clock]
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
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(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
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(Since version Chisel 3.5) Use withClock at Module instantiation