A utility transform used to implement features that are finely distributed through out the target, such as assertion and printf synthesis. This transform preforms most of the circuit modifications and analysis to emit BridgeIOAnnotations and FCCAs directly. For this pass to function correctly, the clock bridge must already be extracted.

For each BridgeTopWiringAnnotation, this transform: 1) Wires out every instance of that signal to a unique port in the top-level module These will be referenced by Bridge FCCAs and will become simulation channels. 2) Determines the source clock (these are now inputs on the top-level module) to which each that port is synchronous

For each clock that is synchronous with at least one output port: 1) Loop that clock back to a new output port (Bridge FCCAs will point at this clock)

Finally emit a BridgeTopWiringOutputAnnotation for each created data-output port.