case class BridgeTopWiringOutputAnnotation(pathlessSource: ReferenceTarget, absoluteSource: ReferenceTarget, topSink: ReferenceTarget, srcClockPort: ReferenceTarget, sinkClockPort: ReferenceTarget) extends Annotation with FAMEAnnotation with Product with Serializable
Provides reference targets to the newly generated top-level IO and a generated output-clock port that output is synchronous to.
- pathlessSource
The original target passed in a BridgeTopWiringAnnotation
- absoluteSource
An absolute reference target to the particular instance of that signal that drives the new output. NB: A single BridgeTopWiringAnnotation will generate as many output annotations as there are instances of the pathless source.
- topSink
The new top-level port the source has been connected to
- srcClockPort
The input clock associated with the source
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Instance Constructors
- new BridgeTopWiringOutputAnnotation(pathlessSource: ReferenceTarget, absoluteSource: ReferenceTarget, topSink: ReferenceTarget, srcClockPort: ReferenceTarget, sinkClockPort: ReferenceTarget)
- pathlessSource
The original target passed in a BridgeTopWiringAnnotation
- absoluteSource
An absolute reference target to the particular instance of that signal that drives the new output. NB: A single BridgeTopWiringAnnotation will generate as many output annotations as there are instances of the pathless source.
- topSink
The new top-level port the source has been connected to
- srcClockPort
The input clock associated with the source
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- val absoluteSource: ReferenceTarget
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- val pathlessSource: ReferenceTarget
- def productElementNames: Iterator[String]
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- val sinkClockPort: ReferenceTarget
- val srcClockPort: ReferenceTarget
- final def synchronized[T0](arg0: => T0): T0
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- val topSink: ReferenceTarget
- def update(renames: RenameMap): Seq[BridgeTopWiringOutputAnnotation]
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