object DefineAbstractClockGate extends Transform with FunctionalPass[CircuitName]
This pass ensures that the AbstractClockGate blackbox is defined in a circuit, so that it can later be instantiated. The blackbox clock gate has the following signature:
module AbstractClockGate(input I, input CE, output O);
I and O are the input and output clocks, respectively, while CE is the enable signal.
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- def analyze(cs: CircuitState): CircuitName
Examine the circuit and store information in an analysis object
Examine the circuit and store information in an analysis object
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- DefineAbstractClockGate → FunctionalPass
- def annotater(cName: CircuitName): (AnnotationSeq) => AnnotationSeq
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Returns a function that, when called, transformes the annotations
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- def renamer(analysis: CircuitName): Option[RenameMap]
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The results of the analysis pass
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Returns a RenameMap that, when applied, appropriately transforms targets
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- final def runTransform(state: CircuitState): CircuitState
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- def transformer(cName: CircuitName): (Circuit) => Circuit
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Returns a function that, when called, transforms the circuit
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- DefineAbstractClockGate → FunctionalPass
- def updateForm(i: CircuitForm): CircuitForm
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(Since version FIRRTL 1.3) Due to confusion, 'dependents' is being renamed to 'optionalPrerequisiteOf'. Override the latter instead.
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