object AutoILATransform extends Transform with DependencyAPIMigration
Finds all FPGADebug annotations deployed throughout the circuit, and wires them to a single ILA instance at the top
of the module hierarchy. The ILA is wrapped in a shim module that preserves the marked signal names and instance
path names in its port list. The shim module instantiates the Xilinx IP only when SYNTHESIS is defined.
This emits an annotation pass generates annotations for two files:
- A ip generation script (tcl) for the ILA IP
- A verilog implementation for the ILA shim. This is verbatim verilog so as to permit using verilog preprocessor macros.
Caveats:
- Targets labelled with the FPGADebug annotation must be synchronous to the simulator's host clock. In practice, the PlatformShim is the only location where it is possible to violate this assumption.
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Type Members
- case class ILAProbe(index: Int, width: Int, name: String, probeTriggers: Int) extends Product with Serializable
Captures per-probe metadata used to build various files related to ILA generation and instantiation
Captures per-probe metadata used to build various files related to ILA generation and instantiation
- index
index of the probe on the ILA.
- width
bit width of the probe
- name
verilog-compatible string that will be used in the wrapper definition and describes the underlying signal being probed.
- probeTriggers
specifies the number of comparators to be generated for this probe. This will be ignored if CONFIG.ALL_PROBE_SAME_MU_CNT is set.
- type InstPath = Seq[String]
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
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- final def asInstanceOf[T0]: T0
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- def clone(): AnyRef
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- protected[lang]
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- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
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- def equals(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef → Any
- def execute(state: CircuitState): CircuitState
- Definition Classes
- AutoILATransform → Transform
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
- def getLogger: Logger
- Definition Classes
- LazyLogging
- def hashCode(): Int
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
- def ilaWrapperFilename(annotations: Seq[Annotation]): String
Generates the filename for the ila wrapper black box.
Generates the filename for the ila wrapper black box.
Can't easily emit verilog black boxes using Golden Gate's file emission system: If using a BBPath anno: the path to verilog may not exist when the BlackBoxSourceHelper runs If using a BBInline anno: the BlackBoxSource helper will write the file out itself. So, use the BBInline anno, and let firrtl do the file emission, but look up Golden Gate's OutputBaseFilename to be consistent.
- returns
The filename of the wrapper
- def invalidates(a: Transform): Boolean
- Definition Classes
- AutoILATransform → DependencyAPIMigration → Transform → DependencyAPI
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val logger: Logger
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- protected
- Definition Classes
- LazyLogging
- def name: String
- Definition Classes
- AutoILATransform → Transform → TransformLike
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
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- Annotations
- @native() @IntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
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- Annotations
- @native() @IntrinsicCandidate()
- def optionalPrerequisiteOf: Seq[Dependency[Emitter]]
- Definition Classes
- AutoILATransform → DependencyAPIMigration → Transform → DependencyAPI
- def optionalPrerequisites: Seq[Nothing]
- Definition Classes
- AutoILATransform → DependencyAPIMigration → Transform → DependencyAPI
- def prerequisites: Seq[TransformDependency]
- Definition Classes
- AutoILATransform → DependencyAPIMigration → Transform → DependencyAPI
- final def runTransform(state: CircuitState): CircuitState
- Definition Classes
- Transform
- final def synchronized[T0](arg0: => T0): T0
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- def toString(): String
- Definition Classes
- AnyRef → Any
- def transform(state: CircuitState): CircuitState
- Definition Classes
- Transform → TransformLike
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
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- @throws(classOf[java.lang.InterruptedException])
- final def wait(): Unit
- Definition Classes
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- @throws(classOf[java.lang.InterruptedException])
Deprecated Value Members
- def dependents: Seq[Dependency[Transform]]
- Definition Classes
- DependencyAPI
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- @deprecated
- Deprecated
(Since version FIRRTL 1.3) Due to confusion, 'dependents' is being renamed to 'optionalPrerequisiteOf'. Override the latter instead.
- def finalize(): Unit
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- protected[lang]
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- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- final def inputForm: CircuitForm
- Definition Classes
- DependencyAPIMigration
- Annotations
- @deprecated
- Deprecated
(Since version FIRRTL 1.3) Use Dependency API methods for equivalent functionality. See: https://bit.ly/2Voppre
- final def outputForm: CircuitForm
- Definition Classes
- DependencyAPIMigration
- Annotations
- @deprecated
- Deprecated
(Since version FIRRTL 1.3) Use Dependency API methods for equivalent functionality. See: https://bit.ly/2Voppre