Type Members

1.  sealed trait BinaryBooleanOp extends AnyRef
2.  class ChannelExcision extends Transform
3.  trait ChannelFlow extends AnyRef
4.  trait ClockChannel extends AnyRef
5.  class Decoupled extends AnyRef
6.  case class DecoupledForwardChannel(readySink: Option[ReferenceTarget], validSource: Option[ReferenceTarget], readySource: Option[ReferenceTarget], validSink: Option[ReferenceTarget]) extends FAMEChannelInfo with Product with Serializable

   Indicates that a channel connection is the forward (valid) half of a decoupled target connection.

   Indicates that a channel connection is the forward (valid) half of a decoupled target connection.

   readySink

   sink port component of the corresponding reverse channel

   validSource

   valid port component from this channel's sources

   readySource

   source port component of the corresponding reverse channel

   validSink

   valid port component from this channel's sinks

   Note

   (readySink, validSource) are on one model, (readySource, validSink) on the other

7.  class EmitAndWrapRAMModels extends Transform
8.  class EmitFAMEAnnotations extends Transform

   A pass that dumps all FAME annotations to a file for debugging.

9.  class ExtractModel extends Transform
10.  trait FAME1Channel extends AnyRef

    ************ PRECONDITIONS: ************* 1.) Ports do not have aggregate types (easy to support if necessary) 2.) There are no collisions among input/output channel names

11.  case class FAME1ClockChannel(name: String, ports: Seq[Port], clockInfo: Seq[RationalClock], clockMFMRs: Seq[Int]) extends FAME1Channel with InputChannel with HasModelPort with ClockChannel with Product with Serializable
12.  trait FAME1DataChannel extends FAME1Channel with HasModelPort
13.  case class FAME1InputChannel(name: String, clockDomainEnable: Expression, ports: Seq[Port], firedReg: DefRegister) extends FAME1DataChannel with InputChannel with Product with Serializable
14.  case class FAME1OutputChannel(name: String, clockDomainEnable: Expression, ports: Seq[Port], firedReg: DefRegister) extends FAME1DataChannel with Product with Serializable
15.  case class FAMEChannelConnectionAnnotation(globalName: String, channelInfo: FAMEChannelInfo, clock: Option[ReferenceTarget], sources: Option[Seq[ReferenceTarget]], sinks: Option[Seq[ReferenceTarget]]) extends Annotation with FAMEAnnotation with HasSerializationHints with Product with Serializable

    An annotation that describes the top-level connectivity of channels on different model instances.

    An annotation that describes the top-level connectivity of channels on different model instances.

    globalName

    a globally unique name for this channel connection

    channelInfo

    describes the type of the channel (Wire, Forward/Reverse Decoupled)

    clock

    the *source* of the clock (if any) associated with this channel

    Note

    The clock source must be a port on the model side of the channel

16.  case class FAMEChannelFanoutAnnotation(channelNames: Seq[String]) extends NoTargetAnnotation with FAMEAnnotation with Product with Serializable

    An annotation that lables a set of FAMEChannelConnectionAnnotations as originating from the same source.

    An annotation that lables a set of FAMEChannelConnectionAnnotations as originating from the same source. For channels sourced by a model (non-bridge) FAMEChannelConnectionAnnotations that fanout should share identical sources. However, channels sourced by bridge currently have their sources param set to None, and so this annotation is necessary to re-associate them.

    channelNames

    The list of fanout channels

17.  sealed trait FAMEChannelInfo extends AnyRef

    Describes the type of the channel (Wire, Forward/Reverse Decoupled)

18.  case class FAMEChannelPortsAnnotation(localName: String, clockPort: Option[ReferenceTarget], ports: Seq[ReferenceTarget]) extends Annotation with FAMEAnnotation with Product with Serializable

    An annotation that describes the ports that constitute one channel from the perspective of a particular module that will be replaced by a simulation model.

    An annotation that describes the ports that constitute one channel from the perspective of a particular module that will be replaced by a simulation model. Note that this describes the channels as they appear locally from within the module, so this annotation will apply to *all* instances of that module.

    Upon creation, this annotation is associated with a particular target RTL module M that will eventually be transformed into a FAME model. This module must only be instantiated at the top level.

    localName

    refers to the name of the channel within the scope of the eventual FAME model. This will be used as the channel’s port name in the model. It will also be used to identify microarchitectural state associated with the channel

    ports

    a list of the ports that are grouped into the channel. The ReferenceTargets should be rooted at M, since this information is local to the module. This is also what associates the annotation with a given module M

19.  class FAMEDefaults extends Transform

    Assumes:

    Assumes:

    • AQB form (target module hierachy matches eventually LI-BDN graph, with connectivity still in place.)
    • Only extant FCCAs are on top-level I/O

    Run after ExtractModel Label all unbound top-level ports as wire channels Label *all* model-to-model connections as wire channels Label all children of the top model to be FAME1 transformed

20.  abstract class FAMEGlobalSignal extends SingleTargetAnnotation[ReferenceTarget] with FAMEAnnotation
21.  case class FAMEHostClock(target: ReferenceTarget) extends FAMEGlobalSignal with Product with Serializable
22.  case class FAMEHostReset(target: ReferenceTarget) extends FAMEGlobalSignal with Product with Serializable
23.  class FAMETransform extends Transform
24.  case class FAMETransformAnnotation(target: ModuleTarget) extends SingleTargetAnnotation[ModuleTarget] with FAMEAnnotation with Product with Serializable

    Indicates that a particular target module from the "AQB" canonical form should be transformed to a FAME model.

    Indicates that a particular target module from the "AQB" canonical form should be transformed to a FAME model.

    target

    Points to the target module to be transformed. Since this is a ModuleTarget, all instances at the top level will be transformed identically.

25.  trait HasModelPort extends AnyRef
26.  class InferModelPorts extends Transform
27.  trait InputChannel extends AnyRef
28.  trait IsMemoryPort extends AnyRef

    ************ PRECONDITIONS: ************* 1.) FAME1 Tranform has been run on all models

29.  class LabelSRAMModels extends Transform
30.  abstract class MemPortAnnotation extends Annotation with FAMEAnnotation
31.  case class ModelReadPort(data: ReferenceTarget, addr: ReferenceTarget, en: ReferenceTarget) extends MemPortAnnotation with Product with Serializable
32.  case class ModelReadWritePort(wmode: ReferenceTarget, rdata: ReferenceTarget, wdata: ReferenceTarget, wmask: ReferenceTarget, addr: ReferenceTarget, en: ReferenceTarget) extends MemPortAnnotation with Product with Serializable
33.  case class ModelWritePort(data: ReferenceTarget, mask: ReferenceTarget, addr: ReferenceTarget, en: ReferenceTarget) extends MemPortAnnotation with Product with Serializable
34.  case class PipeChannel(latency: Int) extends FAMEChannelInfo with Product with Serializable

    Indicates that a channel connection is a pipe with <latency> register stages Setting latency = 0 models a wire

    Indicates that a channel connection is a pipe with <latency> register stages Setting latency = 0 models a wire

    TODO: How to handle registers that are reset? Add an Option[RT]?

35.  class PromoteSubmodule extends Transform

    Takes PromoteSubmodule annotations for instantiations and causes each corresponding instance to be removed; ports are added to the parent module and the submodule is added as a peer instance to all modules instantiating the parent module.

    Takes PromoteSubmodule annotations for instantiations and causes each corresponding instance to be removed; ports are added to the parent module and the submodule is added as a peer instance to all modules instantiating the parent module.

    Module nomenclature: Grandparent = instantiator of parent. Transformed to instantiate child alongside parent, connect. Parent = instantiator of child. Transformed to get port of child IO instead of instantiating child. Child = submodule to be promoted. Does not get transformed.

36.  case class PromoteSubmoduleAnnotation(target: InstanceTarget) extends SingleTargetAnnotation[InstanceTarget] with FAMEAnnotation with Product with Serializable

    Indicates that a particular target instance should be promoted one level in the hierarchy.

    Indicates that a particular target instance should be promoted one level in the hierarchy. The specified instance will be pulled out of its parent module and will reside in its "grandparent" module after the PromoteSubmodule transform has run.

    target

    The instance to be promoted. Note that this must be a *local* instance target, as all instances of the parent module will be transformed identically.

37.  class RAMModelInst extends AnyRef
38.  class ReadPort extends IsMemoryPort
39.  class ReadWritePort extends IsMemoryPort
40.  trait ReadyValidSignal extends AnyRef
41.  case class ReadyValidSink(ref: Expression) extends ReadyValidSignal with Product with Serializable
42.  case class ReadyValidSource(ref: Expression) extends ReadyValidSignal with Product with Serializable
43.  class StaticArbiter extends AnyRef
44.  case class TargetClockChannel(clockInfo: Seq[RationalClock], perClockMFMR: Seq[Int]) extends FAMEChannelInfo with Product with Serializable

    Indicates that a channel connection carries target clocks

    Indicates that a channel connection carries target clocks

    clockInfo

    The user-specified metadata, including a name and a ratio relative to the base clock

    perClockMFMR

    Specifies the minimum number of host cycles between clock edges. This is a property of the clock token schedule, and permits relaxing timing constraints on clock domains with miniumum FMRS (MFMR) > 1.

45.  case class ThreadedMem(nThreads: BigInt, proto: DefMemory) extends Statement with IsDeclaration with Product with Serializable
46.  class TrivialChannelExcision extends Transform
47.  case class VirtualClockChannel(targetClock: Port) extends FAME1Channel with InputChannel with ClockChannel with Product with Serializable
48.  class WritePort extends IsMemoryPort