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  • package midas
    Definition Classes
    root
  • package passes
    Definition Classes
    midas
  • object AutoILATransform extends Transform with DependencyAPIMigration

    Finds all FPGADebug annotations deployed throughout the circuit, and wires them to a single ILA instance at the top of the module hierarchy.

    Finds all FPGADebug annotations deployed throughout the circuit, and wires them to a single ILA instance at the top of the module hierarchy. The ILA is wrapped in a shim module that preserves the marked signal names and instance path names in its port list. The shim module instantiates the Xilinx IP only when SYNTHESIS is defined.

    This emits an annotation pass generates annotations for two files:

    • A ip generation script (tcl) for the ILA IP
    • A verilog implementation for the ILA shim. This is verbatim verilog so as to permit using verilog preprocessor macros.

    Caveats:

    • Targets labelled with the FPGADebug annotation must be synchronous to the simulator's host clock. In practice, the PlatformShim is the only location where it is possible to violate this assumption.
    Definition Classes
    passes
  • ILAProbe

case class ILAProbe(index: Int, width: Int, name: String, probeTriggers: Int) extends Product with Serializable

Captures per-probe metadata used to build various files related to ILA generation and instantiation

index

index of the probe on the ILA.

width

bit width of the probe

name

verilog-compatible string that will be used in the wrapper definition and describes the underlying signal being probed.

probeTriggers

specifies the number of comparators to be generated for this probe. This will be ignored if CONFIG.ALL_PROBE_SAME_MU_CNT is set.

Linear Supertypes
Serializable, Product, Equals, AnyRef, Any
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  1. ILAProbe
  2. Serializable
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new ILAProbe(index: Int, width: Int, name: String, probeTriggers: Int)

    index

    index of the probe on the ILA.

    width

    bit width of the probe

    name

    verilog-compatible string that will be used in the wrapper definition and describes the underlying signal being probed.

    probeTriggers

    specifies the number of comparators to be generated for this probe. This will be ignored if CONFIG.ALL_PROBE_SAME_MU_CNT is set.

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  5. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
  6. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  7. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  8. def ilaPortAssignment: String

    A connection from wrapper port to the ILA instance

  9. val index: Int
  10. def ipConfigString: String

    A string that configures the ILA IP elaboration script for this probe

  11. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  12. val name: String
  13. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  14. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  15. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  16. val probeTriggers: Int
  17. def productElementNames: Iterator[String]
    Definition Classes
    Product
  18. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  19. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  20. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  21. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  22. val width: Int
  23. def wrapperPortDef: String

    A verilog input definition on the generated wrapper module

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable]) @Deprecated
    Deprecated

Inherited from Serializable

Inherited from Product

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Inherited from AnyRef

Inherited from Any

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