Contents:

FireSim Papers

These are papers about FireSim and its internal components/features.

ISCA 2018: FireSim: FPGA-Accelerated, Cycle-Accurate Scale-Out System Simulation in the Public Cloud

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, and Krste Asanović. “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”. In proceedings of the 45th ACM/IEEE International Symposium on Computer Architecture (ISCA’18), Los Angeles, CA, June 2018.
Selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2018”. (link)
Selected as the Communications of the ACM Research Highlights Nominee from ISCA 2018. (link)
Selected for “ISCA@50 25-year Retrospective 1996-2020”. (link)
Paper PDF | Slides PDF | IEEE Xplore | BibTeX

FPL 2018: DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles

Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, and Krste Asanović. “DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles”. In proceedings of the 28th International Conference on Field Programmable Logic & Applications (FPL 2018), Dublin, Ireland, August 2018.
Paper PDF

FPGA 2019: FASED: FPGA-Accelerated Simulation and Evaluation of DRAM

David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanović. “FASED: FPGA-Accelerated Simulation and Evaluation of DRAM”. In proceedings of the 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, February 2019.
Paper PDF | Slides PPTX

IEEE Micro Top Picks 2018: FireSim: FPGA-Accelerated, Cycle-Accurate Scale-Out System Simulation in the Public Cloud

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, and Krste Asanović. “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”. IEEE Micro, vol. 39, no. 3, pp. 56-65, (Micro Top Picks 2018 Issue). May-June 2019.
Article PDF | IEEE Xplore | Micro Top Picks 2018 Introduction

ICCAD 2019: Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration

Qijing Huang, Christopher Yarp, Sagar Karandikar, Nathan Pemberton, Benjamin Brock, Liang Ma, Guohao Dai, Robert Quitt, Krste Asanović, and John Wawrzynek. “Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration”. In proceedings of the 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, November 2019.
Paper PDF | Slides PDF

ICCAD 2019: Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes

Albert Magyar, David T. Biancolin, Jack Koenig, Sanjit Seshia, Jonathan Bachrach, Krste Asanović, “Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes”. In proceedings of the 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Westminster, CO, November 2019.
Paper PDF | Slides PDF

ASPLOS 2020: FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design

Sagar Karandikar, Albert Ou, Alon Amid, Howard Mao, Randy Katz, Borivoje Nikolić, and Krste Asanović, “FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design”. In Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2020), Lausanne, Switzerland, March 2020.
Paper PDF, ACM DL (open-access) | ACM DL | Pre-print PDF | Talk Video on YouTube | Open-source Docs

ISPASS 2021: FireMarshal: Making HW/SW Co-Design Reproducible and Reliable

Nathan Pemberton and Alon Amid. “FireMarshal: Making HW/SW Co-Design Reproducible and Reliable”. In Proceedings of the 2021 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2021.
IEEE Xplore

IEEE Micro 41.4: Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim

David Biancolin, Albert Magyar, Sagar Karandikar, Alon Amid, Borivoje Nikolić, Jonathan Bachrach, and Krste Asanović. “Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim”. IEEE Micro, vol. 41, no. 4, pp. 58-66. July-Aug 2021.
IEEE Xplore

ISCA@50 Retrospective: RETROSPECTIVE: FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud

Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolić, Randy Katz, Jonathan Bachrach, and Krste Asanović. “RETROSPECTIVE: FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud”. In ISCA@50 Retrospective: 1996-2020, Edited by José F. Martínez and Lizy K. John, June 2023.
Retrospective PDF

ISCA 2024: FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs

Joonho Whangbo, Edwin Lim, Chengyi Lux Zhang, Kevin Anderson, Abraham Gonzalez, Raghav Gupta, Nivedha Krishnakumar, Sagar Karandikar, Borivoje Nikolić, Yakun Sophia Shao, Krste Asanović. “FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs”. In Proceedings of the 51st Annual International Symposium on Computer Architecture (ISCA ‘24). July 2024.
IEEE Xplore

User Papers

FireSim has been used in published work across a wide-variety of domains, including computer architecture, systems, networking, security, scientific computing, circuits, design automation, and more. Below are papers that use FireSim in their work (that we know of). Send us an email if you would like your paper listed here.

ISCA 2018: A Hardware Accelerator for Tracing Garbage Collection

Martin Maas (UC Berkeley), Krste Asanović (UC Berkeley), John Kubiatowicz (UC Berkeley). “A Hardware Accelerator for Tracing Garbage Collection”. In proceedings of the 45th ACM/IEEE International Symposium on Computer Architecture (ISCA’18), Los Angeles, CA, June 2018.
Selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2018”.
Paper PDF

MICRO 2018: Composable Building Blocks to Open up Processor Design

Sizhuo Zhang (MIT), Andrew Wright (MIT), Thomas Bourgeat (MIT), Arvind (MIT). “Composable Building Blocks to Open up Processor Design”. In proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’18), Fukuoka, Japan, October 2018.
Selected as one of IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2018”.
Paper PDF

EMC^2 Workshop at HPCA 2019: Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim

Farzad Farshchi (University of Kansas), Qijing Huang (UC Berkeley) and Heechul Yun (University of Kansas). “Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim”. In proccedings of The 2nd Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications, at HPCA 2019, Washington D.C., February 2019.
Paper PDF | Slides PDF

CARRV 2019 Workshop at ISCA 2019: Replicating and Mitigating Spectre Attacks on a Open Source RISC-V Microarchitecture

Abraham Gonzalez (UC Berkeley), Ben Korpan (UC Berkeley), Jerry Zhao (UC Berkeley), Ed Younis (UC Berkeley) and Krste Asanović (UC Berkeley). “Replicating and Mitigating Spectre Attacks on a Open Source RISC-V Microarchitecture”. In proceedings of the Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019), at ISCA 2019, Phoenix, AZ, June 2019.
Paper PDF

CARRV 2019 Workshop at ISCA 2019: Nested-Parallelism PageRank on RISC-V Vector Multi-Processors

Alon Amid (UC Berkeley), Albert Ou (UC Berkeley), Krste Asanović (UC Berkeley) and Borivoje Nikolić (UC Berkeley). “Nested-Parallelism PageRank on RISC-V Vector Multi-Processors”. In proceedings of the Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019), at ISCA 2019, Phoenix, AZ, June 2019.
Paper PDF | Slides PDF

EuroSys 2020: Keystone: An Open Framework for Architecting TEEs

Dayeol Lee (UC Berkeley), David Kohlbrenner (UC Berkeley), Shweta Shinde (UC Berkeley), Dawn Song (UC Berkeley), Krste Asanović (UC Berkeley). “Keystone: An Open Framework for Architecting TEEs”. In proceedings of the 15th European Conference on Computer Systems (EuroSys 2020), Heraklion, Greece, April 2020.
Paper PDF

RTAS 2020: BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors

Farzad Farshchi (University of Kansas), Qijing Huang (UC Berkeley) and Heechul Yun (University of Kansas). “BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors”. In proceedings of the 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), April 2020.
IEEE Xplore

CARRV 2020 Workshop at ISCA 2020: SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine

Jerry Zhao (UC Berkeley), Ben Korpan (UC Berkeley), Abraham Gonzalez (UC Berkeley), and Krste Asanović (UC Berkeley). “SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine”. Fourth Workshop on Computer Architecture Research with RISC-V (CARRV 2020) at the 47th International Symposium on Computer Architecture (ISCA-2020), May 2020.
Paper PDF

IPDPSW 2020: SALSA: A Domain Specific Architecture for Sequence Alignment

Lorenzo Di Tucci (Politecnico di Milano/MIT), Riyadh Baghdadi (MIT), Saman Amarasinghe (MIT), Marco D. Santambrogio (Politecnico di Milano). “SALSA: A Domain Specific Architecture for Sequence Alignment”. In proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), May 2020.
IEEE Xplore

DAC 2020: Invited: Chipyard - Integrated SoC Research and Implementation Environment

Alon Amid (UC Berkeley), David Biancolin (UC Berkeley), Abraham Gonzalez (UC Berkeley), Daniel Grubb (UC Berkeley), Sagar Karandikar (UC Berkeley), Harrison Liew (UC Berkeley), Albert Magyar (UC Berkeley), Howard Mao (UC Berkeley), Albert Ou (UC Berkeley), Nathan Pemberton (UC Berkeley), Paul Rigge (UC Berkeley), Colin Schmidt (UC Berkeley), John Wright (UC Berkeley), Jerry Zhao (UC Berkeley), Jonathan Bachrach (UC Berkeley), Yakun Sophia Shao (UC Berkeley), Krste Asanović (UC Berkeley), Borivoje Nikolić (UC Berkeley). “Invited: Chipyard - Integrated SoC Research and Implementation Environment”. Design Automation Conference (DAC-2020), San Francisco, CA, June 2020.
IEEE Xplore

VLSI 2020: Managing Chip Design Complexity in the Domain-Specific SoC Era

Yunsup Lee (SiFive, Inc.) and Andrew Waterman (SiFive, Inc.). “Managing Chip Design Complexity in the Domain-Specific SoC Era”. In proceedings of the 2020 IEEE Symposium on VLSI Circuits, June 2020.
IEEE Xplore

IEEE SSCL 2020.3: Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28nm FD-SOI

Colin Schmidt (UC Berkeley), Alon Amid (UC Berkeley), John Wright (UC Berkeley), Ben Keller (NVIDIA), Howard Mao (UC Berkeley), Keertana Settaluri (UC Berkeley), Jarno Salomaa (Aalto University), Jerry Zhao (UC Berkeley), Albert Ou (UC Berkeley), Krste Asanović (UC Berkeley), and Borivoje Nikolić (UC Berkeley), “Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28nm FD-SOI”, In IEEE Solid-State Circuits Letters, 3, July 2020.
IEEE Xplore

IEEE Micro 40.4: Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs

Alon Amid (UC Berkeley), David Biancolin (UC Berkeley), Abraham Gonzalez (UC Berkeley), Daniel Grubb (UC Berkeley), Sagar Karandikar (UC Berkeley), Harrison Liew (UC Berkeley), Albert Magyar (UC Berkeley), Howard Mao (UC Berkeley), Albert Ou (UC Berkeley), Nathan Pemberton (UC Berkeley), Paul Rigge (UC Berkeley), Colin Schmidt (UC Berkeley), John Wright (UC Berkeley), Jerry Zhao (UC Berkeley), Yakun Sophia Shao (UC Berkeley), Krste Asanović (UC Berkeley), Borivoje Nikolić (UC Berkeley). “Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs”. In IEEE Micro, vol. 40, no. 4, pp. 10-21, July-Aug 2020.
IEEE Xplore

IEEE TVLSI Dec. 2020: A Dual-Core RISC-V Vector Processor with On-Chip Fine-Grain Power Management in 28nm FD-SOI

John Wright (UC Berkeley), Colin Schmidt (UC Berkeley), Ben Keller (UC Berkeley), Palmer Dabbelt (UC Berkeley), Jaehwa Kwak (UC Berkeley), Vignesh Iyer (UC Berkeley), Nandish Mehta (UC Berkeley), Pi-Feng Chiu (UC Berkeley), Stevo Bailey (UC Berkeley), Krste Asanović (UC Berkeley), and Borivoje Nikolić (UC Berkeley). “A Dual-Core RISC-V Vector Processor with On-Chip Fine-Grain Power Management in 28nm FD-SOI”. IEEE Transactions on VLSI Systems 28(12), December 2020.
IEEE Xplore

ISPASS 2021: COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors

Jerry Zhao (UC Berkeley), Abraham Gonzalez (UC Berkeley), Alon Amid (UC Berkeley), Sagar Karandikar (UC Berkeley) and Krste Asanović (UC Berkeley). “COBRA: A Framework for Evaluating Compositions of Hardware Branch Predictors”. In proceedings of the 2021 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2021.
IEEE Xplore

ISCAS 2021: Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs

Alon Amid (UC Berkeley), Albert Ou (UC Berkeley), Krste Asanović (UC Berkeley), Yakun Sophia Shao (UC Berkeley), Borivoje Nikolić (UC Berkeley). “Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs”. In proceedings of the 2021 IEEE International Symposium on Circuits and Systems (ISCAS), May 2021.
IEEE Xplore

IEEE SP 2021: DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs

Jaewon Hur (Seoul National University), Suhwan Song (Seoul National University), Dongup Kwon (Seoul National University), Eunjin Baek (Seoul National University), Jangwoo Kim (Seoul National University), Byoungyoung Lee (Seoul National University). “DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs”. In proceedings of the 2021 IEEE Symposium on Security and Privacy (SP), May 2021.
IEEE Xplore

CARRV 2021 Workshop at ISCA 2021: ERTOS: Enclaves in Real-Time Operating Systems

Alexander Thomas (UC Berkeley), Stephan Kaminsky (UC Berkeley), Dayeol Lee (UC Berkeley), Dawn Song (UC Berkeley), Krste Asanovic (UC Berkeley). “ERTOS: Enclaves in Real-Time Operating Systems”. Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021) at the 48th International Symposium on Computer Architecture (ISCA-2021), June 2021.
Paper PDF

OSDI 2021: The nanoPU: A Nanosecond Network Stack for Datacenters

Stephen Ibanez (Stanford University), Alex Mallery (Stanford University), Serhat Arslan (Stanford University), Theo Jepsen (Stanford University), Muhammad Shahbaz (Purdue University), Changhoon Kim (Stanford University), and Nick McKeown (Stanford University). “The nanoPU: A Nanosecond Network Stack for Datacenters”. In proceedings of the 15th USENIX Symposium on Operating Systems Design and Implementation (OSDI 21), July 2021.
Paper PDF

USENIX Security 2021: MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design

Gururaj Saileshwar (Georgia Institute of Technology), Moinuddin Qureshi (Georgia Institute of Technology). “MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design”. In proceedings of the 30th USENIX Security Symposium (USENIX Security 21), August 2021.
Paper PDF

ESSCIRC 2021: A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET

Abraham Gonzalez (UC Berkeley), Jerry Zhao (UC Berkeley), Ben Korpan (UC Berkeley), Hasan Genc (UC Berkeley), Colin Schmidt (UC Berkeley), John Wright (UC Berkeley), Ayan Biswas (UC Berkeley), Alon Amid (UC Berkeley), Farhana Sheikh (Intel), Anton Sorokin (Intel), Sirisha Kale (Intel), Mani Yalamanchi (Intel), Ramya Yarlagadda (Intel), Mark Flannigan (Intel), Larry Abramowitz (Intel), Elad Alon (UC Berkeley), Yakun Sophia Shao (UC Berkeley), Krste Asanović (UC Berkeley), Borivoje Nikolić (UC Berkeley). “A 16mm2 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET”. In proceedings of the IEEE 47th European Solid State Circuits Conference (ESSCIRC), September 2021.
IEEE Xplore

MICRO 2021: TIP: Time-Proportional Instruction Profiling

Björn Gottschall (Norwegian University of Science and Technology), Lieven Eeckhout (Ghent University), and Magnus Jahre (Norwegian University of Science and Technology). “TIP: Time-Proportional Instruction Profiling”. In proceedings of the 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO ‘21), October 2021.
MICRO-54 Best paper runner-up.
ACM DL

MICRO 2021: A Hardware Accelerator for Protocol Buffers

Sagar Karandikar (UC Berkeley/Google), Chris Leary (Google), Chris Kennelly (Google), Jerry Zhao (UC Berkeley), Dinesh Parimi (UC Berkeley), Borivoje Nikolic (UC Berkeley), Krste Asanovic (UC Berkeley), and Parthasarathy Ranganathan (Google). “A Hardware Accelerator for Protocol Buffers”. In proceedings of the 54th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO ‘21), October 2021.
MICRO-54 Distinguished Artifact Award Winner.
Selected as an Honorable Mention in IEEE Micro’s “Top Picks from Computer Architecture Conferences, 2021”.
ACM DL

SOSR 2021: NanoTransport: A Low-Latency, Programmable Transport Layer for NICs

Serhat Arslan (Stanford University), Stephen Ibanez (Stanford University), Alex Mallery (Stanford University), Changhoon Kim (Stanford University), and Nick McKeown (Stanford University). “NanoTransport: A Low-Latency, Programmable Transport Layer for NICs”. In Proceedings of the ACM SIGCOMM Symposium on SDN Research (SOSR ‘21), October 2021.
ACM DL

IEEE TC Nov. 2021: A First Look at RISC-V Virtualization from an Embedded Systems Perspective

Bruno Sa (Universidade do Minho), Jose Martins (Universidade do Minho), Sandro Emanuel Salgado Pinto (Universidade do Minho). “A First Look at RISC-V Virtualization from an Embedded Systems Perspective”. In IEEE Transactions on Computers, November 2021.
IEEE Xplore

CCS 2021: Hardware Support to Improve Fuzzing Performance and Precision

Ren Ding (Georgia Institute of Technology), Yonghae Kim (Georgia Institute of Technology), Fan Sang (Georgia Institute of Technology), Wen Xu (Georgia Institute of Technology), Gururaj Saileshwar (Georgia Institute of Technology), and Taesoo Kim (Georgia Institute of Technology). “Hardware Support to Improve Fuzzing Performance and Precision”. In Proceedings of the 2021 ACM SIGSAC Conference on Computer and Communications Security (CCS ‘21), November 2021.
ACM DL

DAC 2021: Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration

Hasan Genc (UC Berkeley), Seah Kim (UC Berkeley), Alon Amid (UC Berkeley), Ameer Haj-Ali (UC Berkeley), Vighnesh Iyer (UC Berkeley), Pranav Prakash (UC Berkeley), Jerry Zhao (UC Berkeley), Daniel Grubb (UC Berkeley), Harrison Liew (UC Berkeley), Howard Mao (UC Berkeley), Albert J. Ou (UC Berkeley), Colin Schmidt (UC Berkeley), Samuel Steffl (UC Berkeley), John Charles Wright (UC Berkeley), Ion Stoica (UC Berkeley), Jonathan Ragan-Kelley (MIT), Krste Asanovic (UC Berkeley), Borivoje Nikolic (UC Berkeley), Yakun Sophia Shao (UC Berkeley). “Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration”. In proceedings of the 2021 58th ACM/IEEE Design Automation Conference (DAC), December 2021.
DAC 2021 Best Paper Award Winner.
IEEE Xplore

HOST 2021: Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware

Austin Harris (University of Texas), Tarunesh Verma (University of Michigan), Shijia Wei (University of Texas), Lauren Biernacki (University of Michigan), Alex Kisil (Agita Labs), Misiker Tadesse Aga (University of Michigan), Valeria Bertacco (University of Michigan), Baris Kasikci (University of Michigan), Mohit Tiwari (University of Texas), Todd Austin (University of Michigan/Agita Labs). “Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware”. In proceedings of the 2021 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), December 2021.
IEEE Xplore

CARRV 2022 Workshop at ISCA 2022: AOS-RISC-V: Towards Always-On Heap Memory Safety

Yonghae Kim (Georgia Tech), Anurag Kar (Georgia Tech), Siddant Singh (Georgia Tech), Ammar A. Ratnani (Georgia Tech), Jaekyu Lee (Arm Research), Hyesoon Kim (Georgia Tech). “AOS-RISC-V: Towards Always-On Heap Memory Safety”. Sixth Workshop on Computer Architecture Research with RISC-V (CARRV 2022) at the 49th International Symposium on Computer Architecture (ISCA-2022), June 2022.
Paper PDF

PASC 2022: Communication bounds for convolutional neural networks

Anthony Chen (University of Michigan), James Demmel (UC Berkeley), Grace Dinh (UC Berkeley), Mason Haberle (New York University), and Olga Holtz (UC Berkeley). “Communication bounds for convolutional neural networks”. In Proceedings of the Platform for Advanced Scientific Computing Conference (PASC ‘22), June 2022.
ACM DL

USENIX Security 2022: Elasticlave: An Efficient Memory Model for Enclaves

Jason Zhijingcheng Yu (National University of Singapore), Shweta Shinde (ETH Zurich), Trevor E. Carlson (National University of Singapore), and Prateek Saxena (National University of Singapore). “Elasticlave: An Efficient Memory Model for Enclaves”. In proceedings of the 31st USENIX Security Symposium (USENIX Security 22), August 2022.
Paper PDF

ACM TACO 20.1: SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V

Hai Jin (Huazhong University of Science and Technology), Zhuo He (Huazhong University of Science and Technology), and Weizhong Qiang (Huazhong University of Science and Technology), “SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V”. In ACM Transactions on Architecture and Code Optimization, 20.1, February 2023.
ACM DL

HPCA 2023: MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks

Seah Kim (UC Berkeley), Hasan Genc (UC Berkeley), Vadim Vadimovich Nikiforov (UC Berkeley), Krste Asanovic (UC Berkeley), Borivoje Nikolic (UC Berkeley), Yakun Sophia Shao (UC Berkeley). “MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks”. In proceedings of the 29th Annual IEEE International Symposium on High-Performance Computer Architecture (HPCA ‘23), February 2023.
IEEE Xplore

ASPLOS 2023: Simulator Independent Coverage for RTL Hardware Languages

Kevin Laeufer (UC Berkeley), Vighnesh Iyer (UC Berkeley), David Biancolin (SiFive, Inc.), Jonathan Bachrach (JITX, Inc.), Borivoje Nikolic (UC Berkeley) and Koushik Sen (UC Berkeley). “Simulator Independent Coverage for RTL Hardware Languages”. In Proceedings of the Twenty-Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2023), Vancouver, Canada, March 2023.
Paper PDF

DATE 2023: Block Group Scheduling: A General Precision-scalable NPU Scheduling Technique with Capacity-aware Memory Allocation

Seokho Lee (Hanyang University), Younghyun Lee (Hanyang University), Hyejun Kim (Yonsei University), Taehoon Kim (Hanyang University), and Yongjun Park (Yonsei University). “Block Group Scheduling: A General Precision-scalable NPU Scheduling Technique with Capacity-aware Memory Allocation”. In Proceedings of the 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE 2023), Antwerp, Belgium, April 2023.
IEEE Xplore

ISPASS 2023: Profiling gem5 Simulator

Johnson Umeike (University of Kansas), Neel Patel (University of Kansas), Alex Manley (University of Kansas), Amin Mamandipoor (University of Kansas), Heechul Yun (University of Kansas), Mohammad Alian (University of Kansas). “Profiling gem5 Simulator”. In Proceedings of the 2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Raleigh, NC, USA, April 2023.
IEEE Xplore

ISC HPC 23 Workshops: Evaluation of HPC Workloads Running on Open-Source RISC-V Hardware

Luc Berger-Vergiat (Sandia National Laboratories), Suma G. Cardwell (Sandia National Laboratories), Ben Feinberg (Sandia National Laboratories), Simon D. Hammond (Sandia National Laboratories), Clayton Hughes (Sandia National Laboratories), Michael Levenhagen (Sandia National Laboratories), and Kevin Pedretti (Sandia National Laboratories). “Evaluation of HPC Workloads Running on Open-Source RISC-V Hardware”. In ISC High Performance 2023 International Workshops. May 2023.
Paper Download

MLArchSys 2023: DOSA: One-Loop DSE for DNN Accelerators Using Differentiable Models

Charles Hong (UC Berkeley), Qijing Huang (NVIDIA), Grace Dinh (UC Berkeley), Yakun Sophia Shao (UC Berkeley). “DOSA: One-Loop DSE for DNN Accelerators Using Differentiable Models”. 2023 ML for Computer Architecture and Systems Workshop (MLArchSys) at the 50th Annual International Symposium on Computer Architecture (ISCA 2023), June 2023.
Paper PDF

MLArchSys 2023: Sample-Efficient Mapspace Optimization for DNN Accelerators with Bayesian Learning

Grace Dinh (UC Berkeley), Iniyaal Kannan (UC Berkeley), Hengrui Luo (Lawrence Berkeley National Lab), Charles Hong (UC Berkeley) Younghyun Cho (UC Berkeley), James Demmel (UC Berkeley), Xiaoye Sherry Li (Lawrence Berkeley National Lab), Yang Liu (Lawrence Berkeley National Lab). “Sample-Efficient Mapspace Optimization for DNN Accelerators with Bayesian Learning”. 2023 ML for Computer Architecture and Systems Workshop (MLArchSys) at the 50th Annual International Symposium on Computer Architecture (ISCA 2023), June 2023.
Paper PDF

ISCA 2023: Profiling Hyperscale Big Data Processing

Abraham Gonzalez (Google/UC Berkeley), Aasheesh Kolli (Google), Samira Khan (Google), Sihang Liu (University of Waterloo), Vidushi Dadu (Google), Sagar Karandikar (UC Berkeley/Google), Jichuan Chang (Google), Krste Asanovic (UC Berkeley), and Parthasarathy Ranganathan (Google). “Profiling Hyperscale Big Data Processing”. In Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA ‘23). June 2023.
ACM DL

ISCA 2023: RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation

Dima Nikiforov (UC Berkeley), Shengjun Chris Dong (UC Berkeley), Chengyi Lux Zhang (UC Berkeley), Seah Kim (UC Berkeley), Borivoje Nikolic (UC Berkeley), and Yakun Sophia Shao (UC Berkeley). “RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation”. In Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA ‘23). June 2023.
ACM DL

ISCA 2023: CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems

Sagar Karandikar (UC Berkeley/Google), Aniruddha N. Udipi (Google), Junsun Choi (UC Berkeley), Joonho Whangbo (UC Berkeley), Jerry Zhao (UC Berkeley), Svilen Kanev (Google), Edwin Lim (Google), Jyrki Alakuijala (Google), Vrishab Madduri (UC Berkeley), Yakun Sophia Shao (UC Berkeley), Borivoje Nikolic (UC Berkeley), Krste Asanovic (UC Berkeley), and Parthasarathy Ranganathan (Google). “CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems”. In Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA ‘23). June 2023.
ACM DL

ISCA 2023: TEA: Time-Proportional Event Analysis

Björn Gottschall (Norwegian University of Science and Technology), Lieven Eeckhout (Ghent University), and Magnus Jahre (Norwegian University of Science and Technology). “TEA: Time-Proportional Event Analysis”. In Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA ‘23). June 2023.
ACM DL

ISCA 2023: Imprecise Store Exceptions

Siddharth Gupta (EPFL), Yuanlong Li (EPFL), Qingxuan Kang (EPFL), Abhishek Bhattacharjee (Yale University), Babak Falsafi (EPFL), Yunho Oh (Korea University), and Mathias Payer (EPFL). “Imprecise Store Exceptions”. In Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA ‘23). June 2023.
ACM DL

IJ-HPCA 37.3: INDIANA—In-Network Distributed Infrastructure for Advanced Network Applications

Sabra Ossen (Indiana University), Jeremy Musser (Indiana University), Luke Dalessandro (Indiana University), and Martin Swany (Indiana University). “INDIANA—In-Network Distributed Infrastructure for Advanced Network Applications”. In The International Journal of High Performance Computing Applications. July 2023.
DOI

OSDI 2023: Security and Performance in the Delegated User-level Virtualization

Jiahao Chen (Shanghai Jiao Tong University), Dingji Li (Shanghai Jiao Tong University), Zeyu Mi (Shanghai Jiao Tong University), Yuxuan Liu (Shanghai Jiao Tong University), Binyu Zang (Shanghai Jiao Tong University), Haibing Guan (Shanghai Jiao Tong University), and Haibo Chen (Shanghai Jiao Tong University). “Security and Performance in the Delegated User-level Virtualization”. In Proceedings of the 17th USENIX Symposium on Operating Systems Design and Implementation (OSDI ‘23). July 2023.
Paper PDF

IEEE TCAD 2023.9: Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models

Burin Amornpaisannon (National University of Singapore), Andreas Diavastos (Universitat Politecnica de Catalunya), Li-Shiuan Peh (National University of Singapore), and Trevor E. Carlson (National University of Singapore). “Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models”. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023.9. September 2023.
IEEE Xplore

IEEE CAL 2023.2: Hardware-Assisted Code-Pointer Tagging for Forward-Edge Control-Flow Integrity

Yonghae Kim (Georgia Tech), Anurag Kar (Georgia Tech), Jaewon Lee (Georgia Tech), Jaekyu Lee (ARM Research), Hyesoon Kim (Georgia Tech). “Hardware-Assisted Code-Pointer Tagging for Forward-Edge Control-Flow Integrity”. In IEEE Computer Architecture Letters (Volume: 22, Issue: 2). September 2023.
IEEE Xplore

IISWC 2023: Balancing Accuracy and Evaluation Overhead in Simulation Point Selection

Björn Gottschall (Norwegian University of Science and Technology), Silvio Campelo de Santana (Norwegian University of Science and Technology), and Magnus Jahre (Norwegian University of Science and Technology). “Balancing Accuracy and Evaluation Overhead in Simulation Point Selection”. In proceedings of the 2023 IEEE International Symposium on Workload Characterization (IISWC 2023), October 2023.
IEEE Xplore

MICRO 2023: AuRORA: Virtualized Accelerator Orchestration for Multi-Tenant Workloads

Seah Kim (UC Berkeley), Jerry Zhao (UC Berkeley), Krste Asanovic (UC Berkeley), Borivoje Nikolic (UC Berkeley), Yakun Sophia Shao (UC Berkeley). “AuRORA: Virtualized Accelerator Orchestration for Multi-Tenant Workloads”. In proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO ‘23), October 2023.
Paper PDF

MICRO 2023: DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators

Charles Hong (UC Berkeley), Qijing Huang (NVIDIA), Grace Dinh (UC Berkeley), Mahesh Subedar (Intel Labs), Yakun Sophia Shao (UC Berkeley). “DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators”. In proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO ‘23), October 2023.
Paper PDF

MICRO 2023: Accelerating Extra Dimensional Page Walks for Confidential Computing

Dong Du (Shanghai Jiao Tong University), Bicheng Yang (Shanghai Jiao Tong University), Yubin Xia (Shanghai Jiao Tong University), Haibo Chen (Shanghai Jiao Tong University). “Accelerating Extra Dimensional Page Walks for Confidential Computing”. In proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO ‘23), October 2023.
Paper PDF

NDSS 2024: BliMe: Verifiably Secure Outsourced Computation with Hardware-Enforced Taint Tracking

Hossam ElAtali (University of Waterloo), Lachlan J. Gunn (Aalto University), Hans Liljestrand (University of Waterloo), and N. Asokan (University of Waterloo/Aalto University). “BliMe: Verifiably Secure Outsourced Computation with Hardware-Enforced Taint Tracking”. In proceedings of the 2024 Network and Distributed System Security Symposium (NDSS 2024). February 2024.
Pre-print PDF

ASPLOS 2024: SIOPMP: Scalable and Efficient I/O Protection for TEEs

Erhu Feng (Shanghai Jiao Tong University), Dahu Feng (Tsinghua University), Dong Du (Shanghai Jiao Tong University), Yubin Xia (Shanghai Jiao Tong University), Wenbin Zheng (Alibaba DAMO Academy), Siqi Zhao (Alibaba DAMO Academy), and Haibo Chen (Shanghai Jiao Tong University). “SIOPMP: Scalable and Efficient I/O Protection for TEEs”. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2024). April 2024.
ACM DL

ASPLOS 2024: Skip It: Take Control of Your Cache!

Shashank Anand (ETH Zurich), Michal Friedman (ETH Zurich), Michael Giardino (ETH Zurich), and Gustavo Alonso (ETH Zurich). “Skip It: Take Control of Your Cache!”. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2024). April 2024.
ACM DL

ASPLOS 2024: Tandem Processor: Grappling with Emerging Operators in Neural Networks

Soroush Ghodrati (UC San Diego), Sean Kinzer (UC San Diego), Hanyang Xu (UC San Diego), Rohan Mahapatra (UC San Diego), Yoonsung Kim (KAIST), Byung Hoon Ahn (UC San Diego), Dong Kai Wang (UIUC), Lavanya Karthikeyan (UC San Diego), Amir Yazdanbakhsh (Google DeepMind), Jongse Park (KAIST), Nam Sung Kim (UIUC), and Hadi Esmaeilzadeh (UC San Diego). “Tandem Processor: Grappling with Emerging Operators in Neural Networks”. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2024). April 2024.
ACM DL

ASPLOS 2024: BeeZip: Towards An Organized and Scalable Architecture for Data Compression

Ruihao Gao (ICT-CAS), Zhichun Li (ICT-CAS), Guangming Tan (ICT-CAS), and Xueqi Li (ICT-CAS). “BeeZip: Towards An Organized and Scalable Architecture for Data Compression”. In Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2024). April 2024.
ACM DL

ISCA 2024: sNPU: Trusted Execution Environments on Integrated NPUs

Erhu Feng (Shanghai Jiao Tong University*), Dahu Feng (Tsinghua University*), Dong Du (Shanghai Jiao Tong University), Yubin Xia (Shanghai Jiao Tong University), Haibo Chen (Shanghai Jiao Tong University). “sNPU: Trusted Execution Environments on Integrated NPUs”. In Proceedings of the 51st Annual International Symposium on Computer Architecture (ISCA ‘24). July 2024.
* Co-first-authors
IEEE Xplore

ISCA 2024: FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching

Jianming Tong (Georgia Tech), Anirudh Itagi (Georgia Tech), Prasanth Chatarasi (IBM Research), Tushar Krishna (Georgia Tech). “FEATHER: A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching”. In Proceedings of the 51st Annual International Symposium on Computer Architecture (ISCA ‘24). July 2024.
IEEE Xplore

VLSI-SoC 2024: A Scalable Hardware Architecture for Efficient Learning of Recurrent Neural Networks at the Edge

Yicheng Zhang (Eindhoven University of Technology), Manil Dev Gomony (Eindhoven University of Technology), Henk Corporaal (Eindhoven University of Technology), and Federico Corradi (Eindhoven University of Technology). “A Scalable Hardware Architecture for Efficient Learning of Recurrent Neural Networks at the Edge”. In proceedings of the 2024 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2024). October 2024.
Pre-print PDF

ICCAD 2024: Sustainable High-Performance Instruction Selection for Superscalar Processors

Saeideh Sheikhpour (Ghent University), David Christoph Metz (Norwegian University of Science and Technology), Erling Jullum (Norwegian University of Science and Technology), Magnus Själander (Norwegian University of Science and Technology), Lieven Eeckhout (Ghent University). “Sustainable High-Performance Instruction Selection for Superscalar Processors”. In proceedings of the 2024 ACM/IEEE International Conference on Computer-Aided Design (ICCAD 2024). October 2024.
Pre-print PDF

ICCAD 2024: RISCSparse: Point Cloud Inference Engine on RISC-V Processor

Shangran Lin (The Chinese University of Hong Kong: Shenzhen), Xinrui Zhu (Chinese University of Hong Kong: Shenzhen), Baohui Xie (The Chinese University of Hong Kong: Shenzhen), Tinghuan Chen (The Chinese University of Hong Kong: Shenzhen), Cheng Zhuo (Zhejiang University), Qi Sun (Zhejiang University), Bei Yu (The Chinese University of Hong Kong). “RISCSparse: Point Cloud Inference Engine on RISC-V Processor”. In proceedings of the 2024 ACM/IEEE International Conference on Computer-Aided Design (ICCAD 2024). October 2024.
Pre-print PDF

MICRO 2024: Stellar: An Automated Design Framework for Dense and Sparse Spatial Accelerators

Hasan Nazim Genc (UC Berkeley), Hansung Kim (UC Berkeley), Prashanth Ganesh (UC Berkeley), Yakun Sophia Shao (UC Berkeley) “Stellar: An Automated Design Framework for Dense and Sparse Spatial Accelerators”. In proceedings of the 57th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO ‘24), November 2024.
Pre-print PDF

RTSS 2024: Per-Bank Bandwidth Regulation of Shared Last-Level Cache for Real-Time Systems

Connor Sullivan (University of Kansas), Alex Manley (University of Kansas), Mohammad Alian (Cornell University), Heechul Yun (University of Kansas). “Per-Bank Bandwidth Regulation of Shared Last-Level Cache for Real-Time Systems”. In proceedings of the 2024 IEEE Real-Time Systems Symposium (RTSS 2024). December 2024.
Pre-print PDF

Slides and Videos for several additional talks from FireSim users can be found on the 2023 FireSim and Chipyard User/Developer Workshop webpage.

Blogs

AWS APN Blog: Leveraging Amazon EC2 F1 Instances for Development and Red Teaming in DARPA’s First-Ever Bug Bounty Program

Kurt Hopfer. Leveraging Amazon EC2 F1 Instances for Development and Red Teaming in DARPA’s First-Ever Bug Bounty Program. AWS APN Blog. May 2021.
Link

NVIDIA Developer Blog: NVDLA Deep Learning Inference Compiler is Now Open Source

Rekha Mukund, Prashant Gaikwad and Mitch Harwell. NVDLA Deep Learning Inference Compiler is Now Open Source. NVIDIA Developer Blog. September 2019.
Link | NVDLA + Deep Learning Inference Compiler on FireSim, GitHub Repo

AWS Compute Blog: Bringing Datacenter-Scale Hardware-Software Co-design to the Cloud with FireSim and Amazon EC2 F1 Instances

Sagar Karandikar, Krste Asanović. Bringing Datacenter-Scale Hardware-Software Co-design to the Cloud with FireSim and Amazon EC2 F1 Instances. AWS Compute Blog. October 2017.
Link | Demo

External Talks/Events

Full-day Tutorial on FireSim and Chipyard at ISCA 2023

Speakers: Sagar Karandikar, Jerry Zhao, Vighnesh Iyer, JunSun Choi, Joonho Whangbo, Dima Nikiforov, Shengjun Kris Dong. Full-day Tutorial on FireSim and Chipyard at ISCA 2023. Orlando, FL, June 2023.
Slides

Latch Up 2023: FireSim: A Scalable Platform for FPGA-Accelerated Simulation, Debugging, and Profiling of RTL Designs

Speaker: Sagar Karandikar. FireSim: A Scalable Platform for FPGA-Accelerated Simulation, Debugging, and Profiling of RTL Designs. Latch Up 2023, Santa Barbara, CA, April 2023.
Video

First FireSim and Chipyard User and Developer Workshop (at ASPLOS 2023)

Speakers: See Program. First FireSim and Chipyard User and Developer Workshop (at ASPLOS 2023). Vancouver, Canada, March 2023.
Workshop Program, Slides, and Videos

Full-day Tutorial on FireSim and Chipyard at ASPLOS 2023

Speakers: Sagar Karandikar, Jerry Zhao, Vighnesh Iyer, Abraham Gonzalez. Full-day Tutorial on FireSim and Chipyard at ASPLOS 2023. Vancouver, Canada, March 2023.
Slides and Videos

Half-day Tutorial on FireSim and Chipyard at HPCA 2023

Speakers: Sagar Karandikar, Jerry Zhao, Abraham Gonzalez. Half-day Tutorial on FireSim and Chipyard at HPCA 2023. Montreal, Canada, February 2023.
Slides

Full-day Tutorial on FireSim and Chipyard at MICRO 2022

Speakers: Sagar Karandikar, Jerry Zhao, Nayiri Krzysztofowicz, Abraham Gonzalez. Full-day Tutorial on FireSim and Chipyard at MICRO 2022. Chicago, IL, October 2022.
Slides

OSCAR: Open-Source Computer Architecture Workshop at ISCA 2022: Chipyard, FireSim, and Hammer: A Push-Button End-to-End Stack for Open-Source Computer Architecture Research

Speakers: Sagar Karandikar, Nayiri Krzysztofowicz. Chipyard, FireSim, and Hammer: A Push-Button End-to-End Stack for Open-Source Computer Architecture Research. OSCAR: Open-Source Computer Architecture Workshop at ISCA 2022, New York, NY, June 2022.
Slides

Full-day Tutorial on FireSim and Chipyard at ISCA 2022

Speakers: Sagar Karandikar, Jerry Zhao, Nayiri Krzysztofowicz, Albert Ou, Abraham Gonzalez. Full-day Tutorial on FireSim and Chipyard at ISCA 2022. New York, NY, June 2022.
Slides

Full-day Tutorial on FireSim and Chipyard at ASPLOS 2022

Speakers: Sagar Karandikar, Jerry Zhao, Nayiri Krzysztofowicz, Abraham Gonzalez. Full-day Tutorial on FireSim and Chipyard at ASPLOS 2022. Lausanne, Switzerland, March 2022.
Slides

Full-day Tutorial on FireSim and Chipyard at MICRO 2021

Speakers: Sagar Karandikar, Jerry Zhao, Abraham Gonzalez, Harrison Liew, James Dunn, David Biancolin, Nathan Pemberton, Albert Ou. Full-day Tutorial on FireSim and Chipyard at MICRO 2021. Virtual, October 2021.
Slides | Video

Full-day Tutorial on FireSim and Chipyard at ISCA 2021

Speakers: Sagar Karandikar, Jerry Zhao, Abraham Gonzalez, Harrison Liew, Nathan Pemberton, Albert Ou, Alon Amid. Full-day Tutorial on FireSim and Chipyard at ISCA 2021. Virtual, June 2021.
Slides

UC Santa Cruz Hardware Systems Collective Seminar: FireSim and FirePerf: Simulating, Debugging, and Profiling RTL Designs with Cloud FPGAs

Speaker: Sagar Karandikar. FireSim and FirePerf: Simulating, Debugging, and Profiling RTL Designs with Cloud FPGAs. UC Santa Cruz Hardware Systems Collective Seminar, Virtual, April 2020.
Video

ASPLOS 2020 Main Conference: FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design

Speaker: Sagar Karandikar. FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design. Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2020), Virtual, March 2020.
Video

2020 Chisel Community Conference:

Speakers: Alon Amid, Sagar Karandikar. Chipyard and FireSim Tutorial. 2020 Chisel Community Conference, Milpitas, CA, January 2020.

Full-day Tutorial on FireSim and Chipyard at MICRO 2019

Speakers: Sagar Karandikar, Jerry Zhao, Howard Mao, Abraham Gonzalez, John Wright, David Biancolin, Nathan Pemberton, Albert Ou, Alon Amid. Full-day Tutorial on FireSim and Chipyard at MICRO 2019. Columbus, OH, October 2019.
Slides

CARRV 2019: Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research

Speaker: Sagar Karandikar. Using FireSim to Enable Agile End-to-End RISC-V Computer Architecture Research. Third Workshop on Computer Architecture Research with RISC-V (CARRV 2019), Phoenix, AZ, June 2019.

Latch-Up 2019: FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud

Speakers: David Biancolin, Alon Amid. FireSim: Open-Source Easy-to-use FPGA-Accelerated Cycle-Exact Hardware Simulation in the Cloud. Latch-Up Conference 2019, Portland, OR, May 2019.

FPGA 2019: FASED: FPGA-Accelerated Simulation and Evaluation of DRAM

Speaker: David Biancolin. FASED: FPGA-Accelerated Simulation and Evaluation of DRAM. 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, February 2019.

2018 RISC-V Summit: Tutorial: Easy-to-use, FPGA-Accelerated Hardware Simulation of RISC-V Hardware Designs with FireSim on Amazon EC2 F1

Speakers: Sagar Karandikar, David Biancolin, Alon Amid. Tutorial: Easy-to-use, FPGA-Accelerated Hardware Simulation of RISC-V Hardware Designs with FireSim on Amazon EC2 F1. 2018 RISC-V Summit, Santa Clara, CA, December 2018.
Slides

2018 Chisel Community Conference: FireSim Tutorial

Speakers: Sagar Karandikar, David Biancolin, Alon Amid. FireSim Tutorial. 2018 Chisel Community Conference, Berkeley, CA, November 2018.
Video

4th Workshop on Open Source Supercomputing (OpenSuCo 4) at Supercomputing 2018: FireSim: Scalable FPGA-accelerated Cycle-Accurate Hardware Simulation in the Cloud

Speaker: Sagar Karandikar. FireSim: Scalable FPGA-accelerated Cycle-Accurate Hardware Simulation in the Cloud. 4th Workshop on Open Source Supercomputing (OpenSuCo 4) at Supercomputing 2018, Dallas, TX, November 2018.

2018 IBM Research Workshop on Architectures for Secure, Cognitive, and Datacenter Computing: FireSim: Scalable FPGA-accelerated Cycle-Accurate Hardware Simulation in the Cloud.

Speaker: Sagar Karandikar. FireSim: Scalable FPGA-accelerated Cycle-Accurate Hardware Simulation in the Cloud. 2018 IBM Research Workshop on Architectures for Secure, Cognitive, and Datacenter Computing, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, November 2018.

ModSim 2018: Workshop on Modeling & Simulation of Systems and Applications: FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-Accurate Hardware Simulation in the Cloud

Speaker: Sagar Karandikar. FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-Accurate Hardware Simulation in the Cloud. ModSim 2018: Workshop on Modeling & Simulation of Systems and Applications, Seattle, WA, August 2018.

USENIX Vail Computer Elements Workshop, 2018: FireSim: Enabling fast, cycle-accurate warehouse-scale architecture research with open hardware and FPGAs in the cloud

Speaker: Sagar Karandikar. FireSim: Enabling fast, cycle-accurate warehouse-scale architecture research with open hardware and FPGAs in the cloud. USENIX Vail Computer Elements Workshop, 2018, Vail, CO, June 2018.

ISCA 2018: FireSim: FPGA-Accelerated, Cycle-Accurate Scale-Out System Simulation in the Public Cloud

Speaker: Sagar Karandikar. FireSim: FPGA-Accelerated, Cycle-Accurate Scale-Out System Simulation in the Public Cloud. 45th ACM/IEEE International Symposium on Computer Architecture (ISCA’18), Los Angeles, CA, June 2018.
Slides PDF | Paper PDF

Stanford DAWN Lab Seminar: FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud

Speaker: Sagar Karandikar. FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. Stanford DAWN Lab Seminar, Stanford, CA, May 2018.

7th RISC-V Workshop: FireSim: Cycle-Accurate Rack-Scale System Simulation using FPGAs in the Public Cloud

Speaker: Sagar Karandikar. FireSim: Cycle-Accurate Rack-Scale System Simulation using FPGAs in the Public Cloud. 7th RISC-V Workshop, Milpitas, CA, November 2017.
Slides | Video