class RAMModelInst extends AnyRef
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- val addrWidth: Int
- val allPorts: Seq[IsMemoryPort { def anno: midas.passes.fame.MemPortAnnotation with java.io.Serializable{def getTargets: Seq[firrtl.annotations.ReferenceTarget]} }]
- final def asInstanceOf[T0]: T0
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- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
- val dataWidth: Int
- def defInst(): WDefInstance
- val depth: BigInt
- def elaborateModel(parentCircuitNS: Namespace): Module
- def emitStatements(clock: WRef, hostReset: WRef): Seq[Statement]
- final def eq(arg0: AnyRef): Boolean
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- def getAddressWidth: (Seq[IsMemoryPort]) => Int
- final def getClass(): Class[_ <: AnyRef]
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- def getDataWidth: (Seq[IsMemoryPort]) => Int
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- def instType(): BundleType
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- final def notifyAll(): Unit
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- def readCmdPort: (Int) => Decoupled
- def readCommand: BundleType
- def readDataPort: (Int) => Decoupled
- def readDataType: UIntType
- val readPorts: Seq[ReadPort]
- def refInst(): WRef
- def resetChannel: Decoupled
- def resolveAndCheckParameter(getParamFunc: (IsMemoryPort) => Int)(memoryPortList: Seq[IsMemoryPort]): Int
- final def synchronized[T0](arg0: => T0): T0
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- final def wait(arg0: Long, arg1: Int): Unit
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- final def wait(): Unit
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- def writeCommand: BundleType
- def writePort: (Int) => Decoupled
- val writePorts: Seq[WritePort]