trait IsMemoryPort extends AnyRef
************ PRECONDITIONS: ************* 1.) FAME1 Tranform has been run on all models
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- abstract def anno: MemPortAnnotation
- abstract def dataPortRT: ReferenceTarget
- abstract def ports: Seq[Port]
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- final def !=(arg0: Any): Boolean
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- final def ##: Int
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- def addrWidth: Int
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- def dataWidth: Int
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- final def getClass(): Class[_ <: AnyRef]
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- def getFieldName(rT: ReferenceTarget): String
- def getSubType(rT: ReferenceTarget): Type
- def hashCode(): Int
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- final def notifyAll(): Unit
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- def portMap: Map[ReferenceTarget, Port]
- def ready(rT: ReferenceTarget): WSubField
- final def synchronized[T0](arg0: => T0): T0
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- final def wait(arg0: Long, arg1: Int): Unit
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- final def wait(arg0: Long): Unit
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- final def wait(): Unit
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