class WritePort extends IsMemoryPort
Linear Supertypes
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- WritePort
- IsMemoryPort
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Visibility
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Instance Constructors
- new WritePort(anno: ModelWritePort, ports: Seq[Port])
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def addrWidth: Int
- Definition Classes
- IsMemoryPort
- val anno: ModelWritePort
- Definition Classes
- WritePort → IsMemoryPort
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def attachChannels(writeCmd: Decoupled): Seq[Statement]
- def bits(rT: ReferenceTarget): WSubField
- Definition Classes
- IsMemoryPort
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
- def dataPortRT: ReferenceTarget
- Definition Classes
- WritePort → IsMemoryPort
- def dataWidth: Int
- Definition Classes
- IsMemoryPort
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef → Any
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
- def getFieldName(rT: ReferenceTarget): String
- Definition Classes
- IsMemoryPort
- def getSubType(rT: ReferenceTarget): Type
- Definition Classes
- IsMemoryPort
- def hashCode(): Int
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- def mTarget: ModuleTarget
- Definition Classes
- IsMemoryPort
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- def portMap: Map[ReferenceTarget, Port]
- Definition Classes
- IsMemoryPort
- val ports: Seq[Port]
- Definition Classes
- WritePort → IsMemoryPort
- def ready(rT: ReferenceTarget): WSubField
- Definition Classes
- IsMemoryPort
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- def toString(): String
- Definition Classes
- AnyRef → Any
- def valid(rT: ReferenceTarget): WSubField
- Definition Classes
- IsMemoryPort
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])