c

midas.models.sram

RegfileChiselRTL

class RegfileChiselRTL extends Module

Linear Supertypes
Module, RawModule, BaseModule, IsInstantiable, HasId, InstanceId, AnyRef, Any
Ordering
  1. Alphabetic
  2. By Inheritance
Inherited
  1. RegfileChiselRTL
  2. Module
  3. RawModule
  4. BaseModule
  5. IsInstantiable
  6. HasId
  7. InstanceId
  8. AnyRef
  9. Any
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new RegfileChiselRTL(depth: Int, dataWidth: Int, nReads: Int, nWrites: Int)

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  8. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  9. val channels: RegfileRTLIO
  10. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  11. final val clock: Clock
    Definition Classes
    Module
  12. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
  13. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  14. val data: Vec[UInt]
  15. val dataWidth: Int
  16. val depth: Int
  17. def desiredName: String
    Definition Classes
    BaseModule
  18. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  19. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  20. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  21. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  22. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  23. def hasSeed: Boolean
    Definition Classes
    HasId
  24. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  25. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  26. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  27. val nReads: Int
  28. val nWrites: Int
  29. final lazy val name: String
    Definition Classes
    BaseModule
  30. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  31. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  32. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  33. def parentModName: String
    Definition Classes
    HasId → InstanceId
  34. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  35. def pathName: String
    Definition Classes
    HasId → InstanceId
  36. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  37. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  38. final val reset: Reset
    Definition Classes
    Module
  39. def suggestName(seed: => String): RegfileChiselRTL.this.type
    Definition Classes
    HasId
  40. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  41. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  42. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  43. def toString(): String
    Definition Classes
    AnyRef → Any
  44. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  45. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  46. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  47. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable]) @Deprecated
    Deprecated
  2. def override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  3. def override_clock_=(rhs: Option[Clock]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  4. def override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  5. def override_reset_=(rhs: Option[Bool]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

Inherited from Module

Inherited from RawModule

Inherited from BaseModule

Inherited from IsInstantiable

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

Ungrouped