class BankedAsyncMemChiselModel extends Module

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Module, RawModule, BaseModule, IsInstantiable, HasId, InstanceId, AnyRef, Any
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Inherited
  1. BankedAsyncMemChiselModel
  2. Module
  3. RawModule
  4. BaseModule
  5. IsInstantiable
  6. HasId
  7. InstanceId
  8. AnyRef
  9. Any
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Visibility
  1. Public
  2. Protected

Instance Constructors

  1. new BankedAsyncMemChiselModel(depth: Int, dataWidth: Int, nReads: Int, nWrites: Int, hostParams: HostParams = BankedAsyncMemChiselModel.HostParams(4, 2, false, true))

Type Members

  1. case class Read(cmd: DecoupledIO[ReadCmd], resp: DecoupledIO[UInt], done: Bool) extends Product with Serializable
  2. case class Write(cmd: DecoupledIO[WriteCmd], done: Bool) extends Product with Serializable

Value Members

  1. final def !=(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  2. final def ##: Int
    Definition Classes
    AnyRef → Any
  3. final def ==(arg0: Any): Boolean
    Definition Classes
    AnyRef → Any
  4. def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
    Attributes
    protected
    Definition Classes
    BaseModule
  5. def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
    Attributes
    protected
    Definition Classes
    BaseModule
  6. var _closed: Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  7. def _compatAutoWrapPorts(): Unit
    Definition Classes
    BaseModule
  8. val allReadsDone: Bool
  9. final def asInstanceOf[T0]: T0
    Definition Classes
    Any
  10. val channels: RegfileModelIO
  11. def circuitName: String
    Attributes
    protected
    Definition Classes
    HasId
  12. final val clock: Clock
    Definition Classes
    Module
  13. def clone(): AnyRef
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
  14. val compileOptions: CompileOptions
    Definition Classes
    RawModule
  15. def desiredName: String
    Definition Classes
    BaseModule
  16. final def eq(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  17. def equals(that: Any): Boolean
    Definition Classes
    HasId → AnyRef → Any
  18. final def getClass(): Class[_ <: AnyRef]
    Definition Classes
    AnyRef → Any
    Annotations
    @native() @IntrinsicCandidate()
  19. def getCommands: Seq[Command]
    Attributes
    protected
    Definition Classes
    RawModule
  20. def getModulePorts: Seq[Data]
    Attributes
    protected[chisel3]
    Definition Classes
    BaseModule
  21. def hasSeed: Boolean
    Definition Classes
    HasId
  22. def hashCode(): Int
    Definition Classes
    HasId → AnyRef → Any
  23. def instanceName: String
    Definition Classes
    BaseModule → HasId → InstanceId
  24. final def isInstanceOf[T0]: Boolean
    Definition Classes
    Any
  25. val nPhysReads: Int
  26. val nPhysWrites: Int
  27. final lazy val name: String
    Definition Classes
    BaseModule
  28. final def ne(arg0: AnyRef): Boolean
    Definition Classes
    AnyRef
  29. final def notify(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  30. final def notifyAll(): Unit
    Definition Classes
    AnyRef
    Annotations
    @native() @IntrinsicCandidate()
  31. def parentModName: String
    Definition Classes
    HasId → InstanceId
  32. def parentPathName: String
    Definition Classes
    HasId → InstanceId
  33. def pathName: String
    Definition Classes
    HasId → InstanceId
  34. val physReadCmds: Vec[ReadCmd]
  35. val physReadResps: Vec[UInt]
  36. val physWriteCmds: Vec[WriteCmd]
  37. def portsContains(elem: Data): Boolean
    Attributes
    protected
    Definition Classes
    BaseModule
  38. def portsSize: Int
    Attributes
    protected
    Definition Classes
    BaseModule
  39. val rBankMaxSize: Int
  40. val reads: IndexedSeq[Read]
  41. final val reset: Reset
    Definition Classes
    Module
  42. def suggestName(seed: => String): BankedAsyncMemChiselModel.this.type
    Definition Classes
    HasId
  43. final def synchronized[T0](arg0: => T0): T0
    Definition Classes
    AnyRef
  44. final def toAbsoluteTarget: IsModule
    Definition Classes
    BaseModule → InstanceId
  45. final def toNamed: ModuleName
    Definition Classes
    BaseModule → InstanceId
  46. def toString(): String
    Definition Classes
    AnyRef → Any
  47. final def toTarget: ModuleTarget
    Definition Classes
    BaseModule → InstanceId
  48. val wBankMaxSize: Int
  49. final def wait(arg0: Long, arg1: Int): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  50. final def wait(arg0: Long): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  51. final def wait(): Unit
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.InterruptedException])
  52. val writes: IndexedSeq[Write]
  53. val writesDoneOrFinishing: Bool

Deprecated Value Members

  1. def finalize(): Unit
    Attributes
    protected[lang]
    Definition Classes
    AnyRef
    Annotations
    @throws(classOf[java.lang.Throwable]) @Deprecated
    Deprecated
  2. def override_clock: Option[Clock]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  3. def override_clock_=(rhs: Option[Clock]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  4. def override_reset: Option[Bool]
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

  5. def override_reset_=(rhs: Option[Bool]): Unit
    Attributes
    protected
    Definition Classes
    Module
    Annotations
    @deprecated
    Deprecated

    (Since version Chisel 3.5) Use withClock at Module instantiation

Inherited from Module

Inherited from RawModule

Inherited from BaseModule

Inherited from IsInstantiable

Inherited from HasId

Inherited from InstanceId

Inherited from AnyRef

Inherited from Any

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