class RegfileChiselModel extends Module
Linear Supertypes
Ordering
- Alphabetic
- By Inheritance
Inherited
- RegfileChiselModel
- Module
- RawModule
- BaseModule
- IsInstantiable
- HasId
- InstanceId
- AnyRef
- Any
- Hide All
- Show All
Visibility
- Public
- Protected
Instance Constructors
Value Members
- final def !=(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- final def ##: Int
- Definition Classes
- AnyRef → Any
- final def ==(arg0: Any): Boolean
- Definition Classes
- AnyRef → Any
- def IO[T <: Data](iodef: => T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T
- Attributes
- protected
- Definition Classes
- BaseModule
- def _bindIoInPlace(iodef: Data)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Unit
- Attributes
- protected
- Definition Classes
- BaseModule
- var _closed: Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def _compatAutoWrapPorts(): Unit
- Definition Classes
- BaseModule
- final def asInstanceOf[T0]: T0
- Definition Classes
- Any
- def bitwise(a: Seq[Bool], b: Seq[Bool], f: (Bool, Bool) => Bool): Seq[Bool]
- val channels: RegfileModelIO
- def circuitName: String
- Attributes
- protected
- Definition Classes
- HasId
- final val clock: Clock
- Definition Classes
- Module
- def clone(): AnyRef
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.CloneNotSupportedException]) @native() @IntrinsicCandidate()
- val compileOptions: CompileOptions
- Definition Classes
- RawModule
- val data: Vec[UInt]
- val dataWidth: Int
- val depth: Int
- def desiredName: String
- Definition Classes
- BaseModule
- val done: Bool
- final def eq(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- def equals(that: Any): Boolean
- Definition Classes
- HasId → AnyRef → Any
- final def getClass(): Class[_ <: AnyRef]
- Definition Classes
- AnyRef → Any
- Annotations
- @native() @IntrinsicCandidate()
- def getCommands: Seq[Command]
- Attributes
- protected
- Definition Classes
- RawModule
- def getModulePorts: Seq[Data]
- Attributes
- protected[chisel3]
- Definition Classes
- BaseModule
- def hasSeed: Boolean
- Definition Classes
- HasId
- val has_reset_token: Bool
- def hashCode(): Int
- Definition Classes
- HasId → AnyRef → Any
- def instanceName: String
- Definition Classes
- BaseModule → HasId → InstanceId
- final def isInstanceOf[T0]: Boolean
- Definition Classes
- Any
- val nReads: Int
- val nWrites: Int
- final lazy val name: String
- Definition Classes
- BaseModule
- final def ne(arg0: AnyRef): Boolean
- Definition Classes
- AnyRef
- final def notify(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- final def notifyAll(): Unit
- Definition Classes
- AnyRef
- Annotations
- @native() @IntrinsicCandidate()
- def parentModName: String
- Definition Classes
- HasId → InstanceId
- def parentPathName: String
- Definition Classes
- HasId → InstanceId
- def pathName: String
- Definition Classes
- HasId → InstanceId
- def portsContains(elem: Data): Boolean
- Attributes
- protected
- Definition Classes
- BaseModule
- def portsSize: Int
- Attributes
- protected
- Definition Classes
- BaseModule
- def prioritize(reqs: Seq[Bool]): Seq[Bool]
- val raddr: UInt
- val rdata: UInt
- val read_cmds_done_next_cycle: Bool
- val read_resps_done_next_cycle: Bool
- val reads_cmd_addr: IndexedSeq[UInt]
- val reads_cmd_can_fire: Seq[Bool]
- val reads_cmd_fire: Seq[Bool]
- val reads_cmd_fired: Seq[Bool]
- val reads_cmd_ready: Seq[Bool]
- val reads_cmd_valid: IndexedSeq[Bool]
- val reads_resp_data: Seq[UInt]
- val reads_resp_fire: Seq[Bool]
- val reads_resp_fired: Seq[Bool]
- val reads_resp_ready: IndexedSeq[Bool]
- val reads_resp_valid: Seq[Bool]
- final val reset: Reset
- Definition Classes
- Module
- val reset_token: Bool
- def suggestName(seed: => String): RegfileChiselModel.this.type
- Definition Classes
- HasId
- final def synchronized[T0](arg0: => T0): T0
- Definition Classes
- AnyRef
- final def toAbsoluteTarget: IsModule
- Definition Classes
- BaseModule → InstanceId
- final def toNamed: ModuleName
- Definition Classes
- BaseModule → InstanceId
- def toString(): String
- Definition Classes
- AnyRef → Any
- final def toTarget: ModuleTarget
- Definition Classes
- BaseModule → InstanceId
- def updateState(fired: Bool, fire: Bool): Unit
- val waddr: UInt
- final def wait(arg0: Long, arg1: Int): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(arg0: Long): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- final def wait(): Unit
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.InterruptedException])
- val wdata: UInt
- val wen: Bool
- val writes_cmd_addr: IndexedSeq[UInt]
- val writes_cmd_can_fire: Seq[Bool]
- val writes_cmd_data: IndexedSeq[UInt]
- val writes_cmd_en: IndexedSeq[Bool]
- val writes_cmd_fire: Seq[Bool]
- val writes_cmd_fired: Seq[Bool]
- val writes_cmd_ready: Seq[Bool]
- val writes_cmd_valid: IndexedSeq[Bool]
- val writes_done_next_cycle: Bool
Deprecated Value Members
- def finalize(): Unit
- Attributes
- protected[lang]
- Definition Classes
- AnyRef
- Annotations
- @throws(classOf[java.lang.Throwable]) @Deprecated
- Deprecated
- def override_clock: Option[Clock]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_clock_=(rhs: Option[Clock]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset: Option[Bool]
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation
- def override_reset_=(rhs: Option[Bool]): Unit
- Attributes
- protected
- Definition Classes
- Module
- Annotations
- @deprecated
- Deprecated
(Since version Chisel 3.5) Use withClock at Module instantiation