package xdc

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Type Members

  1. trait IsPostLink extends AnyRef

    In hierarchal FPGA flows, like EC2 F1's, additional levels of path are introduced once a partition has been linked into the larger design.

    In hierarchal FPGA flows, like EC2 F1's, additional levels of path are introduced once a partition has been linked into the larger design. These indicate to the XDC emission pass whether an additional path should be appended to references that appear in XDC snippets based on whether the constraints will be applied before or after this linking phase.

  2. trait IsPreLink extends AnyRef
  3. sealed trait RAMStyle extends AnyRef
  4. case class XDCAnnotation(destinationFile: XDCDestinationFile, formatString: String, argumentList: ReferenceTarget*) extends Annotation with XDCAnnotationConstants with DontTouchAllTargets with Product with Serializable

    Encode a string to be emitted to an XDC file with specifiers derived from ReferenceTargets (RTs).

    Encode a string to be emitted to an XDC file with specifiers derived from ReferenceTargets (RTs). RTs are called out in the format string using "{}" a la Python. This makes the emitted XDC more robust against the module hierarchy manipulations (such as promotion/extraction and linking) that Golden Gate performs.

    For example: XDCAnnotation("get_pins -of [get_clocks {}]", clockRT)

    Would eventually emit: get_pins -of [get_clocks absolute/path/to/clock]

    Here the emission pass by default creates a full instance path to the reference to avoid multiple matches.

    Restrictions: 1. Multiple specifiers in a string are permitted. However, to simplify emission under more complex duplication conditions, all RTs must share the same explicit root module (i.e their module parameter is the same). . 2. Specifiers currently cannot point at aggregates. This will be resolved in a future PR.

  5. sealed trait XDCDestinationFile extends AnyRef

    All Golden-Gate-known output XDC files extend this.

  6. case class XDCPathToCircuitAnnotation(preLinkPath: Option[String], postLinkPath: Option[String]) extends NoTargetAnnotation with Product with Serializable

    Provides the absolute paths to firrtl-emitted module in the context of the FPGA project before and after linking.

    Provides the absolute paths to firrtl-emitted module in the context of the FPGA project before and after linking. If the firrtl-emitted module is the top-level, set the path to None.

Value Members

  1. object RAMStyleHint
  2. object RAMStyles

    Some rough guidance, based on Ultrascale+, is provided in the scala doc for each hint.

    Some rough guidance, based on Ultrascale+, is provided in the scala doc for each hint. Consult the Xilinx UGs for your target architecture and the synthesis UG (UG901).

  3. object SpecifyXDCCircuitPaths
  4. object XDC extends XDCAnnotationConstants

    Chisel-side sugar for emitting XDCAnnotations.

    Chisel-side sugar for emitting XDCAnnotations.

    For example, to tell Vivado not to optimize away a node:

    val myUsefulWire = Wire(<...>)
    // Note, (currently) calling dontTouch(myUsefulWire) does not get passed through to Vivado.
    XDC(XDCFiles.Synthesis, "set_property DONT_TOUCH [get_cells {}]", myUsefulWire)
  5. object XDCFiles

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