trait IsPostLink extends AnyRef

In hierarchal FPGA flows, like EC2 F1's, additional levels of path are introduced once a partition has been linked into the larger design. These indicate to the XDC emission pass whether an additional path should be appended to references that appear in XDC snippets based on whether the constraints will be applied before or after this linking phase.

Self Type
IsPostLink with XDCDestinationFile
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  1. final def !=(arg0: Any): Boolean
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  2. final def ##: Int
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  3. final def ==(arg0: Any): Boolean
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  4. final def asInstanceOf[T0]: T0
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  5. def clone(): AnyRef
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  6. final def eq(arg0: AnyRef): Boolean
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  7. def equals(arg0: AnyRef): Boolean
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  8. final def getClass(): Class[_ <: AnyRef]
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  9. def hashCode(): Int
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  10. final def isInstanceOf[T0]: Boolean
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  11. final def ne(arg0: AnyRef): Boolean
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  12. final def notify(): Unit
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  13. final def notifyAll(): Unit
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    @native() @IntrinsicCandidate()
  14. def preLink: Boolean
  15. final def synchronized[T0](arg0: => T0): T0
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  16. def toString(): String
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  17. final def wait(arg0: Long, arg1: Int): Unit
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  18. final def wait(arg0: Long): Unit
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  19. final def wait(): Unit
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  1. def finalize(): Unit
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