Type Members

1.  class BIGToken extends Bundle
2.  class BigTokenToNICTokenAdapter extends Module
3.  class BlockDevBridge extends BlackBox with Bridge[HostPortIO[BlockDevBridgeTargetIO], BlockDevBridgeModule]
4.  class BlockDevBridgeModule extends BridgeModule[HostPortIO[BlockDevBridgeTargetIO]]
5.  class BlockDevBridgeTargetIO extends Bundle
6.  class DromajoBridge extends BlackBox with Bridge[HostPortIO[SerializableTileTraceIO], DromajoBridgeModule]

   Blackbox that is instantiated in the target

7.  class DromajoBridgeModule extends BridgeModule[HostPortIO[SerializableTileTraceIO]] with StreamToHostCPU
8.  class GroundTestBridge extends BlackBox with Bridge[HostPortIO[GroundTestBridgeTargetIO], GroundTestBridgeModule]
9.  class GroundTestBridgeModule extends BridgeModule[HostPortIO[GroundTestBridgeTargetIO]]
10.  class GroundTestBridgeTargetIO extends Bundle
11.  class HostToNICToken extends Bundle
12.  class HostToNICTokenGenerator extends Module
13.  class NICBridge extends BlackBox with Bridge[HostPortIO[NICTargetIO], SimpleNICBridgeModule]
14.  class NICTargetIO extends Bundle
15.  class NICToHostToken extends Bundle
16.  class NICTokenToBigTokenAdapter extends Module
17.  class ReadyValidLast extends Bundle
18.  class SimpleNICBridgeModule extends BridgeModule[HostPortIO[NICTargetIO]] with StreamToHostCPU with StreamFromHostCPU
19.  class TSIBridge extends BlackBox with Bridge[HostPortIO[TSIBridgeTargetIO], TSIBridgeModule]
20.  class TSIBridgeModule extends BridgeModule[HostPortIO[TSIBridgeTargetIO]]
21.  case class TSIBridgeParams(memoryRegionNameOpt: Option[String]) extends Product with Serializable

    Class which parameterizes the TSIBridge

    Class which parameterizes the TSIBridge

    memoryRegionNameOpt, if unset, indicates that firesim-fesvr should not attempt to write a payload into DRAM through the loadmem unit. This is suitable for target designs which do not use the FASED DRAM model. If a FASEDBridge for the backing AXI4 memory is present, then memoryRegionNameOpt should be set to the same memory region name which is passed to the FASEDBridge. This enables fast payload loading in firesim-fesvr through the loadmem unit.

22.  class TSIBridgeTargetIO extends Bundle
23.  class TracerVBridge extends BlackBox with Bridge[HostPortIO[TracerVTargetIO], TracerVBridgeModule]

    Target-side module for the TracerV Bridge.

24.  class TracerVBridgeModule extends BridgeModule[HostPortIO[TracerVTargetIO]] with StreamToHostCPU
25.  class TracerVTargetIO extends Bundle
26.  class UARTBridge extends BlackBox with Bridge[HostPortIO[UARTBridgeTargetIO], UARTBridgeModule]
27.  class UARTBridgeModule extends BridgeModule[HostPortIO[UARTBridgeTargetIO]]
28.  class UARTBridgeTargetIO extends Bundle
29.  case class UARTKey(uParams: UARTParams, div: Int) extends Product with Serializable